Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Medium speed multiples data

Abstract: Synchronization can be acquired between a transmitting node and a receiving node on a time division multiple access communication link without the necessity for additional data bits in the data stream, by correlating the number of errors detected in any interval as revealed by the forward error correction field. Both synchronization bits and stuffing bits can be located without using any external frame timing information. Substantial bandwidth savings is achieved by the technique, which can be applied for arbitrary combinations of the number of input ports, the number of data bits per group, and the number of parity bits generated per group.

Circuits for detecting framing bits in a t.d.m. bit stream

Abstract: A framing circuit is disclosed for detecting framing bits in a t.d.m. bit stream having an extended DS1 framing format. The circuit comprises a RAM for storing in respect of each of the 772 time channels the five most recent information bits of the time channel and three other, candidate, bits which represent the likelihood that the particular time channel carries the framing bit pattern. The current and five stored information bits of each time channel are checked to detect the six-bit framing bit pattern. The candidate bits have their value increased or decreased, within predetermined limits, in dependence upon whether or not a phase of the framing bit pattern is detected, and the updated information and candidate bits are stored in the RAM. The modification of the candidate bits in this manner is effected in only every third 772-bit frame. A framing signal is produced in dependence upon the candidate bits.

Circuit and method for internal refresh counter

Abstract: A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

Abstract: A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade-offs. The redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators with clock-gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low-power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.

Full flash analog-to-digital converter

Abstract: A full flash analog-to-digital converter comprises a plurality of comparators for comparing an analog input voltage with respective reference voltages, a first-stage encoder for generating low-order bits based on output signals from the comparators, a second-stage encoder for generating high-order bits based on the low-order bits generated by the first-stage encoder, the first-stage encoder comprising a circuit for generating a complement bit of the highest-order bit of the low-order bits generated by the first-stage encoder, and the second-stage encoder comprising a circuit for generating the high-order bits based on the highest-order bit and the complement bit.