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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


Papers
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Journal ArticleDOI
TL;DR: A 12-bit 50MS/s asynchronous rail-to-rail Pipeline-SAR ADC that achieves low-power, high-resolution and high-speed operation without calibration is presented.

13 citations

Proceedings ArticleDOI
01 Nov 2010
TL;DR: In this paper, an ultra-low voltage operation of 0.5 V, 5-bit Flash ADC has been developed and achieved an ENOB of 4.2-bit at a conversion rate of 600 MS/s.
Abstract: An ultra-low voltage operation of 0.5 V, 5-bit Flash ADC has been developed and achieved an ENOB of 4.2-bit at a conversion rate of 600 MS/s. It consumes only 1.2 mW and attained an ultra-low FoM of 160 fJ/conv. steps at an ERBW of 200 MHz. A forward body bias technique and gate-interpolated double-tail latched comparator with variable delay method to compensate the mismatch voltage are introduced.

13 citations

Patent
Joshua Posamentier1
05 Oct 2006
TL;DR: In this article, a multi-channel analog-to-digital converter (ADC) is proposed, in which the ADC sequentially converts analog values that are input from different analog sensors, separate sample-and-hold circuits may be used to read all the analog values at the same time.
Abstract: In a multi-channel analog-to-digital converter (ADC), in which the ADC sequentially converts analog values that are input from different analog sensors, separate sample-and-hold circuits may be used to read all the analog values at the same time, and the ADC may then sequentially convert the values from each sample-and-hold circuit. This approach allows a single ADC to be used in time-critical applications that require all the analog sensor values to be measured at the same time.

13 citations

Proceedings Article
01 Jan 2000
TL;DR: This paper deals with the design and implementation of an 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter using a conventional 0.5µm self-aligned, double polysilicon bipolar process with maximum unity gain cutoff frequency fTof 25GHz.
Abstract: This paper deals with the design and implementation of an 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter using a conventional 0.5µm self-aligned, double polysilicon bipolar process with maximum unity gain cutoff frequency f T of 25GHz. The high-speed and high-resolution A/D converter has applications in direct IF sampling receivers for wideband communications systems. The converter occupies an area of 2.5mm×3.5mm including bonding pads and exhibits a better than 7-bit ENOB with an input signal frequency of 200MHz and at a sampling rate of 1-Gsample/s. The maximum power dissipation of the ADC is 2.5W using a 5V power supply.

13 citations

Proceedings ArticleDOI
01 Oct 2015
TL;DR: This paper presents a bidirectional neural interface, consisting of 12-channel low-noise amplifiers, channel-level neural feature extraction and proportional-integral-derivative (PID) controller, voltage and current mode analog-to-digital converters (ADC), and 12- channel multi-mode stimulators.
Abstract: This paper presents a bidirectional neural interface, consisting of 12-channel low-noise amplifiers, channel-level neural feature extraction and proportional-integral-derivative (PID) controller, voltage and current mode analog-to-digital converters (ADC), and 12-channel multi-mode stimulators. The neural amplifier features a wide-band from 0.5Hz to 10kHz with a noise floor of 3.02μVrms. The input stage has been designed for high stimulation voltage tolerance, and fast stimulation artifact recovery. The digitally assisted, analog parallel feature extraction processor features an ultra low power consumption while performing 1) neural signal energy extraction in programmable frequency band and time window, or 2) action potential detection using a current-mode time-amplitude window discriminator. A programmable PID controller has been implemented at the channel-level for closed-loop operation. A 640nW 8-bit current-mode ADC featuring a FoM of 10.7fJ/conv-step at a sampling rate of 250kSps has been designed for action potential digitization, and a voltage-mode SAR ADC with a ENOB of 9.1 and FoM of 34.2fJ/conv-step has been implemented for neural features and local field potential digitizations. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4mA and a compliance voltage up to +/-5V in arbitrary channel configuration. The chip has been fabricated in 0.18μm HV-CMOS technology, occupying a silicon area of 2.2 mm2. The whole chip dissipates 276μW on average. Bench testing, in-vitro and in-vivo experimental results are presented in this paper.

13 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147