Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Frame transmission system

Abstract: In a frame transmission system for transmitting multi-frames of a DS3.C-bit parity frame system as prescribed in American National Standard and also in Proposed Contribution to CCITT (ITU-T), C1-bits assigned to the prior art DS3.C-bit parity frame, i.e., 3×3=9 C-bits (fixed bits) for the 2nd, 6th and 7th channels, are used as control bits of DS2 level signal for intrinsic purposes. These bits may be processed in their entirely in the same manner as with the prior art control bits.

CMOS flash analog to digital converter compensation

Abstract: An analog-to-digital converter (ADC) is provided. The analog-to-digital converter includes a plurality of differential comparators. For each of the plurality of differential comparators the ADC receives differential input signals and differential reference signals and generates an output signal. The ADC also includes a self-calibration circuit to receive from each of the plurality of differential comparators the output signal. In response to the output signal, the self-calibration circuit generates a self-calibration signal. The ADC further includes an adjustable reference signal generator to provide the differential reference signals based on the self-calibration signal.

A 10-Bit Multichannel Digitizer ASIC for Detectors in Particle Physics Experiments

Abstract: The design and measurement results of a multi-channel power scalable 10-bit digitizer ASIC developed for the luminosity detector at the future linear colliders (ILC/CLIC) are discussed. The 8 channel prototype with different modes of output data serialization was designed and fabricated in a 0.35 μm CMOS technology. The ASIC works for sampling rates from about 10 kS/s to 25 MS/s (50 MS/s in single channel mode) allowing linear scaling of ADCs and serializer power consumption (0.8 mW/MS/s ADC core, 1.2 mW/MS/s total per channel). A wide spectrum of static and dynamic measurements confirm very good ADC resolution (ENOB = 9.7 bits), excellent channel uniformity and negligible crosstalk. To profit from non-continuous detector operation in linear collider experiments and to save power consumption, fast periodic power pulsing is implemented.

Method and system for asynchronous successive approximation register (sar) analog-to-digital converters (adcs)

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

A low–power 16–channel AD converter and digital processor ASIC

Abstract: The extreme particle density in the detectors for high-energy physics experiments set new demands on the readout electronics in terms of resolution, density and power consumption These requirements are beyond the present capability of commercial-off-the-shelf components and call for ASICs that embed in a single chip the circuits to digitise, process, compress and store the information of a high number of channels In this paper we present an ASIC that responds to these needs, including in a single chip 16 low-power 10-bit 25-MSPS A/D converters, a data processor and 800-Kbit of memory The chip, which is implemented in a 025 µm CMOS technology, has an area of 64mm2and a power consumption of 320mW when the 16 channels are running at 10MHz rate The measurements show a resolution better than 95 ENOB on all channels and a channel-to-channel crosstalk below -65dB The techniques adopted in the front-end and back-end design of the circuit, to limit the impact of the digital noise on the ADC performance and the channel-to-channel crosstalk, are also presented