Topic
Effective number of bits
About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.
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01 Jan 2005
TL;DR: Using oversampling and frequency shifts techniques, along with a synchronous rotating reference frame based PLL, an accurate and fast tracking resolver-to-digital converter is presented.
Abstract: In this paper, an all-digital resolver-to-digital converter is presented Using oversampling and frequency shifts techniques, along with a synchronous rotating reference frame based PLL, an accurate and fast tracking resolver-to-digital converter is presented With the use of all these combined techniques, and using a standard DSP with a 10 bits ADC, resolutions of up to 12 bits are feasible This paper presents the main techniques, simulation and experimental results
13 citations
TL;DR: The time-domain comparator of the TDADC is realized with only one delay line consisting of a digitally controlled delay line and a voltage-controlled delay line, therefore, the linearity degradation due to the mismatch between multiple delay lines can be avoided.
Abstract: A 100-kS/s time-domain analog-to-digital converter (TDADC) with successive approximation register architecture provides 8.3 effective bits. The time-domain comparator of the TDADC is realized with only one delay line consisting of a digitally controlled delay line and a voltage-controlled delay line. Therefore, the linearity degradation due to the mismatch between multiple delay lines can be avoided. The TDADC has been implemented in a 0.11- $\mu\hbox{m}$ CMOS process with a 0.127- $\hbox{mm}^{2}$ active silicon area. The TDADC consumes 1.7 $\mu\hbox{W}$ from a 0.6-V supply voltage.
13 citations
01 Jan 2014
TL;DR: This work proposes a matrix completion based formulation that can also reduce the energy consumption for sensing and test its method with state-of-the-art CS based techniques and finds that the reconstruction accuracy from the method is significantly better and that too at considerably less energy consumption.
Abstract: In Wireless Body Area Networks (WBAN) the energy consumption is dominated by sensing and communication. Previous Compressed Sensing (CS) based solutions to EEG tele-monitoring over WBAN's could only reduce the communication cost. In this work, we propose a matrix completion based formulation that can also reduce the energy consumption for sensing. We test our method with state-of-the-art CS based techniques and find that the reconstruction accuracy from our method is significantly better and that too at considerably less energy consumption. Our method is also tested for post-reconstruction signal classification where it outperforms previous CS based techniques. At the heart of the system is an Analog to Information Converter (AIC) implemented in 65nm CMOS technology. The pseudorandom clock generator enables random under-sampling and subsequent conversion by the 12-bit Successive Approximation Register Analog to Digital Converter (SAR ADC). AIC achieves a sample rate of 0.5 KS/s, an ENOB 9.54 bits, and consumes 108 nW from 1 V power supply.
13 citations
Patent•
16 Jul 2001TL;DR: In this paper, a method and system for powering down an analog-to-digital converter (ADC) into a sleep mode is presented, where the ADC receives a normal set of pulses for a serial clock signal of the ADC, and the ADC outputs converted data requested by a user through a serial interface.
Abstract: A method and system for powering down an analog-to-digital converter (“ADC”) into a sleep mode are disclosed. If the ADC receives a normal set of pulses for a serial clock signal of the ADC, a serial interface controller outputs converted data requested by a user through a serial interface. Also, if the ADC receives a sleep set of pulses for the serial clock signal, a state machine of the ADC powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level. Furthermore, if the ADC is in the sleep mode and the ADC receives a wake-up set of pulses for the serial clock signal, the state machine powers back up the ADC from the sleep mode.
13 citations
01 Nov 2012
TL;DR: The ADC uses a dynamic two-stage comparator with a current source to improve linearity, a digital SAR control logic, bootstrapped sampling switches with body effect reduction, and a charge redistribution differential DAC with a monotonic capacitor switching procedure where the metal-metal capacitor unit is only 1fF for high power efficiency.
Abstract: In this paper, a design of an asynchronous differential SAR ADC is presented. The ADC uses a dynamic two-stage comparator with a current source to improve linearity, a digital SAR control logic, bootstrapped sampling switches with body effect reduction, and a charge redistribution differential DAC with a monotonic capacitor switching procedure where the metal-metal capacitor unit is only 1fF for high power efficiency. At a sample rate of 50MS/s and a supply voltage of 1V, the 9-bit SAR ADC achieves an ENOB of 8.84 bit and consumes 45 µW, resulting in an energy efficiency of 2.01 fJ/conversion-step. The circuits are designed and simulated with parasitic models using a commercially available 28nm bulk CMOS process.
13 citations