Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

A CMOS 6-mW 10-bit 100-MS/s two-step ADC

Abstract: A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power consumption, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The accuracy of the comparators is improved by offset calibration. The gain accuracy and the linearity of the residue amplifier are enhanced by digital background calibration. The ADC consumes 6 mW from a 1 V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34 bits. The FOM is 100 fJ·V per conversion-step.

Method and system for allocating convolutional encoded bits into symbols before modulation for wireless communication

Abstract: A method and corresponding apparatus for encoding a sequence of bits for transmission as symbols, some of the bit positions of the symbols having a higher bit error rate than other bit positions. A plurality of sequences of bits is provided using a convolutional encoder, in response to a sequence of input bits, each sequence of bits being defined by a predetermined generator polynomial having a predetermined level of sensitivity to puncturing. Then the bits of each sequence of bits are mapped to symbol positions based on the level of sensitivity of the generator polynomial defining the sequence of bits. With interleaving, the mapping of bits of each sequence of bits to symbol positions can precede a symbol interleaving step, or it can follow a bit interleaving step.

Si 3 N 4 -Based Integrated Optical Analog Signal Processor and Its Application in RF Photonic Frontend

Abstract: Digital signal processing has achieved great success in the field of signal processing over the past several decades. However, as the bandwidth requirement increases, the power consumption and effective number of bits (ENOB) of the analog-to-digital convertor (ADC) have become bottlenecks. One solution is returning to analog and applying microwave photonic technologies, which shows potential for multiband signal processing. In this paper, a programmable integrated analog photonic signal processor based on cascaded Mach-Zehnder interferometers (MZIs) and a channelized filter has been proposed. Different shapes of the signal processor can be acquired for different applications. The highest processing resolution is 143 MHz, and the processing range of the signal processor can be higher than 112.5 GHz. An application of the signal processor for the signal extraction in a radio frequency (RF) photonic frontend operating from L-band to K-band is presented.

Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits

Abstract: We propose a CMOS Analog Vector-Matrix Multiplier for Deep Neural Networks, implemented in a standard single-poly 180 nm CMOS technology. The learning weights are stored in analog floating-gate memory cells embedded in current mirrors implementing the multiplication operations. We experimentally verify the analog storage capability of designed single-poly floating-gate cells, the accuracy of the multiplying function of proposed tunable current mirrors, and the effective number of bits of the analog operation. We perform system-level simulations to show that an analog deep neural network based on the proposed vector-matrix multiplier can achieve an inference accuracy comparable to digital solutions with an energy efficiency of 26.4 TOPs/J, a layer latency close to $100~\mu \text{s}$ and an intrinsically high degree of parallelism. Our proposed design has also a cost advantage, considering that it can be implemented in a standard single-poly CMOS process flow.

Multi-level encoding system

Abstract: An encoder providing on a single terminal of a circuit package a composite serial data stream containing both stored data bits of a multistage binary memory and a clock signal needed for decoding the data. A parallel to serial converter serially shifts the stored binary data bits to an output thereof in response to clock pulses of an internal clock, and a logic circuit responsive to both the internal clock and the serial binary data from the converter generates first, second and third signals of amplitudes discernibly different from one another respectively in response to 1-state data bits, 0-state data bits and the termination of clock pulses. Two fixed inputs to the converter respectively provide a 1-state start bit at the beginning of the set of data bits and a 0-state stop bit at the end of the set of data bits for purposes of decoding. An amplitude discriminating decoder uses the periodic third signals and the start and stop bits to decode the serial data.