Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

Abstract: We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 25-bit to 705-bit The ADC is manufactured in a 90 nm CMOS technology, with a core area of 085 mm × 035 mm, a 12 V supply for the core and 18 V for the input switches It has an effective number of bits (ENOB) of 705-bit, and a power dissipation of 85 mW at 60 MS/s

A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Abstract: A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

Parallel adder circuit with sign bit decoder for multiplier

Abstract: A parallel adder circuit includes a partial product adding circuit for adding one-bit partial products together in order total to a plurality of partial products, and sign bit decoder circuit for decoding sign bits of a given bit number to provide a total sum of the sign bits, and supply this total sum to the partial product adding circuit at given bits. In a multiplier utilizing Booth's algorithm, a decoder circuit is used for decoding sign bits of the partial product to provide the total sum of all the sign bits, and a decoded output is supplied to the partial product adding circuit. Therefore, the number of higher bit inputs can be reduced and the number of full adders in the partial product adding circuit can be decreased.

An energy-efficient 1MSps 7µW 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm

Abstract: Current trends constantly increase the need for ultra-low power solutions for the embedded and portable hardware. One circuit component required in wide range of devices is the analog-to-digital converter (ADC). In this paper we propose an extremely energy-efficient successive approximation register (SAR) ADC, in which we have overcome the limitations of conventional approaches through topological improvements. Further, advances include a novel bootstrapped track and hold (T/H) circuitry. Statistical simulations indicate an ADC with a figure of merit (FOM) of 11.9 fJ per conversion step, and an effective number of bits (ENOB) of 9.2, operating close to Nyquist frequency, sampling at 1 Msps. To put it into perspective, consuming only 7 pJ/sample, this ADC is able to work at its maximum speed for more than 40 years with the total energy of a single alkaline AA battery.

A 10-bit 20 MS/s successive approximation register analog-to-digital converter using single-sided DAC switching method for control application

Abstract: In this paper 10-bit 20MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented control application as a part of the biological signal acquisition system. By applying single-sided switching method that reduces DAC switching energy, the proposed SAR ADC achieves less power consumption. Also, asynchronous control logic is used which doesn't need an external high frequency clock to drive ADC. Measured results show that at sampling rate of 20 MS/s, the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 70.2 dB, a signal-to-noise and distortion ratio (SNDR) of 56.35 dB, an effective number of bits (ENOB) of 9.067 bits, a differential nonlinearity (DNL) of 1.2 LSB, an integral nonlinearity (INL) of 1.54 LSB and a power consumption of 910 μW. The overall chip area is only 0.57 mm2 with a small ADC core area of 0.171 mm2.