Topic
Effective number of bits
About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.
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Patent•
11 Apr 1975TL;DR: In this paper, a receiver of n-bit data words, each consisting of k information bits and (n-1) redundancy bits, comprises three error detectors receiving the incoming bit stream in parallel with one another and with a shift register of a transfer circuit, the three detectors being triggered by timing pulses fed to them in staggered relationship from a clock circuit extracting synchronizing signals from the bit stream.
Abstract: A receiver of n-bit data words, each consisting of k information bits and (n-1) redundancy bits, comprises three error detectors receiving the incoming bit stream in parallel with one another and with a shift register of a transfer circuit, the three error detectors being triggered by timing pulses fed to them in staggered relationship from a clock circuit extracting synchronizing signals from the bit stream. In normal operation, the middle detector generates a recurrent no-error output signal which has no effect upon the cadence of the timing pulses. If either of the two other detectors emits such a no-error output signal in response to a forward or a backward slip by a predetermined number of bits h, the clock circuit is reset to compensate for the slip. The emission of an output signal from any error detector causes the readout of the received bits from the shift register in the transfer circuit.
13 citations
TL;DR: An auto-ranging ADC with a mechanism to keep the structure stable that emulates more quantization levels than that allowed by the number of comparators is proposed.
Abstract: Multibit feedback, being one way of lowering DeltaSigma modulators power consumption, has a major obstacle: the number of components in the internal analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Nevertheless, the number of comparators in the ADC can be significantly reduced depending on the order of noise-shaping and the oversampling ratio. In this paper, we propose an auto-ranging algorithm with a mechanism to keep the structure stable that emulates more quantization levels than that allowed by the number of comparators. As the recourse to segmented DACs allows lowering the complexity of the mismatch shaping encoder, the auto-ranging ADC brings the benefits of multibit feedback without the usual increase in size and power consumption. The internal number of bits in DeltaSigma modulators is no more restricted by the difficulty of building the flash ADC with a low voltage supply.
13 citations
15 Feb 1999
TL;DR: In this paper, a two-step CMOS subranging ADC (CSA) architecture is proposed, where a coarse comparator bank determines which subset of fine reference taps from a resistor ladder should be passed (without amplification or subtraction from the ADC input) to a fine comparator banks by an analog multiplexer (AMUX).
Abstract: In a two-step CMOS subranging ADC (CSA), a coarse comparator bank determines which subset of fine reference taps from a resistor ladder should be passed (without amplification or subtraction from the ADC input) to a fine comparator bank by an analog multiplexer (AMUX). This CSA provides advantages over previously-reported variations of this architecture. These advantages include absolute value signal processing, an extended settling period for the fine references, a fully differential topology, and a front-end sample-and-hold amplifier (SHA). As a result of these features, this ADC achieves 9.5 ENOB Nyquist performance at 75 mW and two-clock-cycle conversion latency.
13 citations
Proceedings Article•
01 Jan 2019TL;DR: In this article, the authors present a faster and more efficient VCO-based ADC architecture based on an improved high-speed, low-power ring oscillator and an asynchronous counting strategy.
Abstract: Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs are able to benefit directly from improved digital performance [1]; however, the resolution and sampling rate of state-of-the-art VCO-based designs are insufficient for most applications. This paper presents a faster and more efficient VCO-based ADC architecture based on an improved high-speed, low-power ring oscillator and an asynchronous counting strategy. The architecture is 8× time-interleaved and combined with on-chip calibration. The design is implemented in 28nm CMOS and achieves 45.2dB SNDR (7.2 ENOB) near Nyquist at 5GS/s while consuming only 22.7mW, resulting in a Walden FOM of 30.5fJ/conv-step. The core area is only 0.023mm 2. These results demonstrate that VCO-based ADCs are a viable choice for next-generation Ethernet and high-speed wireless communication.
13 citations
10 May 1990-Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment
TL;DR: A 12-bit analog-to-digital converter circuit for nuclear spectroscopy applications was developed using a digital signal processor (DSP) as the central processing element.
Abstract: A 12-bit analog-to-digital converter (ADC) circuit for nuclear spectroscopy applications was developed using a digital signal processor (DSP) as the central processing element.
The DSP runs a program that builds the distribution function of data collected by the ADC (the multichannel analyzer algorithm) and simultaneously corrects the ADC differential nonlinearity (DNL) by the sliding scale method. The acquisition routine runs in ≃4 μs.
The conversion time, when the faster versions of the ADC are used, is well below 10 μs. The resulting DNL is better than 0.4% and the integral nonlinearity <0.002%.
13 citations