Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

A silicon bipolar 4-bit 1-Gsample/s full Nyquist A/D converter

Abstract: A four-bit silicon bipolar analog-to-digital converter (ADC) which is operational at the full Nyquist input frequency up to 1 Gsample/s (Gs/s) is discussed. The effective bit number at 1 Gs/s reduces to 3.5 bits on Nyquist conditions. The 3-dB large-signal analog bandwidth is 800 MHz and the maximum sampling rate reaches 2 Gs/s and beyond. The converter is built up by stacking of two three-bit subcircuits. The ADC architecture relies on a balanced structure mixing conventional flash-converter elements with analog encoding. Total power consumption is 2.4 W. Standard silicon bipolar technology is used without self-alignment. >

Low weight data encoding for minimal power delivery impact

Abstract: A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.

Analysis and optimization of a SAR ADC with attenuation capacitor

Abstract: The conventional binary weighted array SAR ADC is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even requiring extra effort to design and simulate full custom sub-fF capacitors. This paper presents the design and the optimization of an asynchronous SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. A 10-bit prototype has been fabricated in a 0.13-μm CMOS technology. At 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversion-step. This efficiency is comparable to the best results published so far and it's the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an area of only 0.045 mm 2 .

A low noise CMOS image sensor with a 14-bit two-step single-slope ADC and a column self-calibration technique

Abstract: In this paper, a low-noise CMOS Image Sensor (CIS) based on a 14-bit Two-Step Single-Slope ADC (TS SS ADC) and a column self-calibration technique is proposed. The TS SS ADC is good for the video system which requires fast operation because its conversion speed is faster than the Single Slope ADC (SS ADC) by more than 10 times. However, there are a lot of errors in the circuit operation on the connection point between the coarse block and the fine block due to the 2-step composition of the TS SS ADC. This makes it difficult to implement the TS SS ADC into the high resolution more than 10-bit and the product. In order to improve the drawbacks of TS SS ADC, a new 4-input comparator is discussed. Further, a column self-calibration technique to reduce the Fixed Pattern Noise (FPN) is also described. The chip has been fabricated by Samsung 0.13μm CIS technology. The measured conversion time of the ADC is 17μs and the high frame rate of 120 frames/s (fps) is achieved at the VGA resolution. The measured column FPN is 0.38LSB, and it is much lower than the other reported ones.

Serial data interface apparatus and method for detecting an input word length and selecting an operating mode accordingly

Abstract: An apparatus and a method for controlling a mode of operation of a data converter is based on a length of an input word signal to the data converter. The apparatus includes a bit counter that counts the number of bits in the word received by the data converter and provides a word length signal corresponding to the number of bits in the word, and a mode selector that receives the word length signal and selects an operational mode of the data converter based on the word length signal. The method includes steps of counting the number of bits in the word, and selecting a mode of operation of the data converter based on the number of bits in the word.