Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Method and system for application of unequal error protection to uncompressed video for transmission over wireless channels

Abstract: A method and system of wireless communication is provided which involves inputting information bits, wherein certain bits have higher importance level than other bits, and applying unequal protection to the bits at different importance levels. As such, important bits are provided with more protection for transmission and error recovery. Applying unequal protection involves using skewed constellations such that more important bits are provided with more error recovery protection.

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS

Abstract: This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.

Decoding system and method for digital communications

Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.

Error correction system for n bits using error correcting code designed for fewer than n bits

Abstract: A computer system includes an error detection and correction system for detecting and correcting single-bit errors, two-adjacent-bit errors, and four-adjacent-bit errors. Two identical error detection and correction (EDC) circuits are connected to the system memory array, and each EDC circuit is connected to half of the data bits in alternating pairs. Each EDC circuit detects single-bit errors and two-adjacent-bit errors. The EDC circuits are connected to alternating pairs of data bits so that errors of up to four adjacent bits are actually detected and corrected, two bits by the first EDC circuit and two bits by the second. Thus, if one of the x4 DRAMs in a memory array fails, each erroneous data bit from the DRAM is corrected to its original value, and the failure of the DRAM is registered.

130-GSa/s photonic analog-to-digital converter with time stretch preprocessor

Abstract: In this letter, we demonstrate a photonic analog-to-digital converter with time stretch (TS) preprocessor that has a sampling rate of 130 GSa/s. The system has a signal-to-noise ratio (SNR) exceeding seven effective number of bits over a 1-GHz bandwidth at 18 GHz. We present an analytical model of the SNR in the TS preprocessor which shows that over the specified bandwidth, the SNR is limited by the amplified spontaneous emission beat noise.