Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Determining ADC effective number of bits via histogram testing

Abstract: A new application for one of the widely known A/D converter (ADC) dynamic testing methods, namely the histogram method, is discussed. After computing the transition voltages of the ADC transfer characteristics, the effective number of bits is computed. Simulation shows that this method more accurately characterizes the ADC used for arbitrary input signals, compared to the fast Fourier transform (FFT) and sine-fit methods which characterize the ADC in the light of an input sinusoid. The technique outperforms sinewave fitting as it gives more accurate results, while avoiding convergence problems of the iterative curve fitting algorithm. The FFT method was verified to be the least accurate. Simulation indications that the histogram method is better than the sine-fit method are presented. >

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

Abstract: This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of $83~\mu \text {W}$ . The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s.

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable- $g_{m}$ Opamp

Abstract: A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variable- variable-gm opamp. The ADC is implemented in 0.18 mum CMOS technology and occupies a die area of 0.86 mm2. The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, -66.2 dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply.

Implementation of multipliers in programmable arrays

Abstract: Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided a method of multiplying a first number by a second number by use of an array of processing devices, each of said processing devices having a plurality of data inputs, a plurality of data outputs, and an instruction input for control of the function of the processing device, wherein said processing devices and an input for the first number and an input for the second number are interconnected by a freely configurable interconnect, and wherein each processing device calculates a partial product for multiplication of one or more bits of the first number with one or more bits of the second number, and for each processing device: the value received at the instruction input is determined by one or more bits of the first number; data inputs are provided by m bits of the second number, and, if appropriate, a carry input to add a carry from a less significant partial product and/or a summation input to sum all the partial products of the same significance; data outputs are provided as a summation output containing the least significant m bits of the partial product and a carry output containing any more significant bits of the partial product.

Error-resilient transmission of 3D models

Abstract: In this article, we propose an error-resilient transmission method for progressively compressed 3D models. The proposed method is scalable with respect to both channel bandwidth and channel packet-loss rate. We jointly design source and channel coders using a statistical measure that (i) calculates the number of both source and channel coding bits, and (ii) distributes the channel coding bits among the transmitted refinement levels in order to maximize the expected decoded model quality. In order to keep the total number of bits before and after applying error protection the same, we transmit fewer triangles in the latter case to accommodate the channel coding bits. When the proposed method is used to transmit a typical model over a channel with a 10p packet-loss rate, the distortion (measured using the Hausdorff distance between the original and the decoded models) is reduced by 50p compared to the case when no error protection is applied.