Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Jitter requirements of the sampling clock in software radio receivers

Abstract: The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.

Noise sensitivity of the ADC histogram test

Abstract: In the paper, the authors consider the performance of histogram-based analog to digital converter (ADC) testing under the assumption of input-equivalent wideband noise, which models either noise sources inside the device or unwanted disturbances corrupting the stimulus signal employed for carrying out the test. Theoretical relationships are presented which allow the design of the test parameters needed to meet a given test accuracy. Moreover, it is shown, that the histogram test is effective in providing information on the deterministic behavior of the tested device and that it can be made insensitive to the effects of input-equivalent noise. Finally, the obtained results are employed to determine the test performance in estimating the device effective number of bits, and simulations results are provided which validate the theoretical derivations.

26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme

Abstract: Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.

Management of sensors in computer systems

Abstract: A method processes the outputs of a discrete sensor in a computer system. An initial value mask is applied to each one of the offset bits in the output of the discrete sensor. An initial value is obtained for each one of the offset bits in the output of the discrete sensor according to the initial value mask. It is next determined whether or not the offset bits in the output of the discrete sensor includes both initialization offset bits and transition offset bits. If the offset bits include both initialization offset bits and transition bits, only the initialization bits of an incoming mask corresponding to the output of the discrete sensor are reset.

A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

Abstract: A 10.3 GS/s ADC with 5 GHz input BW and 6 bit resolution in 90 nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6 dB SNDR) for a 100 MHz input signal and 5.1 ENOB (32.4 dB SNDR) for a 5 GHz input (Nyquist) with phase offset correction across the interleaved array.