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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


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Journal Article
TL;DR: A novel ADC is described, consisting in its simplest and fastest version of a parallel ADC supplying the most significant bits, plus several suitably-connected difference amplifiers in which the input signal undergoes successive folding.
Abstract: A novel ADC is described, consisting in its simplest and fastest version of a parallel ADC supplying the most significant bits, plus several suitably-connected difference amplifiers in which the input signal undergoes successive folding. Their common output is fed into another parallel ADC which supplies the least significant bits. The conversion rate is of the order of 400 MHz for eight bits. Several versions are described, yielding different trade-offs between speed and the number of discriminators employed.

55 citations

Patent
12 Jun 2004
TL;DR: An analog-to-digital (ADC) converter circuit that converts an analog input signal into a digital output circuit includes a calibration coefficient computation circuit for computing calibration coefficients of a calibration filter as discussed by the authors.
Abstract: An analog-to-digital (ADC) converter circuit that converts an analog input signal into a digital output circuit includes a calibration coefficient computation circuit for computing calibration coefficients of a calibration filter. The calibration coefficient computation circuit includes a switching device adapted to switch the analog input signal delivered to the ADC circuit between on and off states, and includes a pseudo-random signal generator adapted to input a pseudo-random signal to the ADC circuit. During a start-up phase of the ADC circuit, the ADC circuit, the switching device turns off the analog input signal to the ADC circuit, the pseudo-random signal generator inputs a pseudo-random signal into the ADC circuit, and the calibration coefficient computation circuit computes the calibration coefficients of the calibration filter. This ADC circuit configuration reduces startup time for the calibration filter to only a few clock cycles.

55 citations

Patent
25 Jul 2002
TL;DR: In this paper, an apparatus for retransmitting data at a retransmission request from a receiver by a transmitter in a CDMA mobile communication system including a turbo encoder with a given coding rate was presented.
Abstract: An apparatus for retransmitting data at a retransmission request from a receiver by a transmitter in a CDMA mobile communication system including a turbo encoder with a given coding rate and initially transmitting systematic bits and parity bits obtained by encoding the data by the turbo encoder using one modulation mode among a plurality of modulation modes. A controller determines a modulation mode to be used between the transmitter and the receiver in response to the retransmission request. A distributor distributes coded bits obtained by encoding the data at the coding rate into systematic bits and parity bits. A selector selects coded bits transmittable by the determined modulation mode among the systematic bits and the parity bits at the initial transmission, if the determined modulation mode is different from the modulation mode used at initial transmission. A modulator modulates the transmittable coded bits into modulated symbols according to the determined modulation mode.

55 citations

Patent
27 Jul 1981
TL;DR: In this article, the information blocks are catenated by inserting separation blocks of n 2 bits there between, selected so that the (d,k)-constraint is satisfied over the boundary between any two information words.
Abstract: A system for block encoding words of a digital signal achieves a maximum of error compaction and ensures reliability of a self-clocking decoder, while minimizing any DC in the encoded signal. Data words of m bits are translated into information blocks of n 1 bits (n 1 >m) that satisfy a (d,k)-constraint in which at least d "0" bits, but no more than k "0" bits occur between successive "1" bits. The information blocks are catenated by inserting separation blocks of n 2 bits therebetween, selected so that the (d,k)-constraint is satisfied over the boundary between any two information words. For each information word, the separation block that will yield the lowest net digital sum value is selected. Then, the encoded signal is modulated as an NRZ-M signal in which a "1" becomes a transition and a "0" becomes an absence of a transition. A unique synchronizing block is inserted periodically. A decoder circuit, using the synchronizing blocks to control its timing, disregards the separation blocks, but detects the information blocks and translates them back into reconstituted data words of m bits. The foregoing technique can be used to advantage in recording digitized music on an optical disc.

55 citations

Journal ArticleDOI
TL;DR: A bulk voltage trimming offset calibration technique is presented for flash analog-to-digital converters (ADCs) that improves the accuracy of flash ADCs while not impairing their high-speed performance.
Abstract: A bulk voltage trimming offset calibration technique is presented for flash analog-to-digital converters (ADCs). Offset calibration is achieved by digitally adjusting the bulk voltages of the preamplifier input devices. Without introducing additional capacitive loading in the analog path, this technique improves the accuracy of flash ADCs while not impairing their high-speed performance. A 4-bit ADC in 90-nm CMOS with the proposed technique achieves 3.71 effective number of bits (ENOB) at 5-GS/s sampling rate with 2.5-GHz effective resolution bandwidth (ERBW). The calibration generally improves ENOB by approximately 0.5 bit after calibration. The ADC consumes 86 mW at 5 GS/s with a 2.5-GHz input achieving a 1.32-pJ/convstep figure of merit. The ADC occupies 0.135-mm2 chip area.

55 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147