Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Digital broadcasting system and method

Abstract: Apparatus and method of achieving diversity in reception of plural digital broadcast signals. A stream of a complete set of code bits is generated from one or more sources of data bits. A first Critical Subset of code bits is chosen or selected for a first channel (e.g. a specified puncturing pattern is applied to the stream of a complete set of code sets). A second (e.g. alternative) Critical Subset of code bits is chosen or selected for a second channel (e.g. a second or alternative puncturing pattern is chosen for the second channel). Further alternative Critical Subsets may be chosen for any additional channels. All the channels are transmitters, some can incorporate time delay to achieve temporal diversity. Moreover, the order of transmitting the code bits on each channel can be it different (for example, the interleaving depths can be different). At the receiver, the stream of Critical Subsets of code bits for all of the channels are simultaneously received and a reconstruction of a complete set of code bits accomplished and the reconstructed code and may be inserted into a single Viterbi decoder. Various weighting functions and reconstruction algorithms are disclosed.

Circuit and method for multilevel signal decoding, descrambling, and error detection

Abstract: At least two level detectors compare a multilevel signal to respective prescribed voltage levels to produce corresponding streams of bits. These bit streams are repeatedly delayed in respective digital delay lines, and bits from the digital delay lines are output in parallel to multilevel decoder logic. The multilevel decoder logic converts the parallel bits into a plurality of corresponding two-level decoded bits and performs error detections for an invalid transition in the multilevel signal. The decoded bits may be descrambled and block decoded.

A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS

Abstract: A 7-bit 1.5-GS/s analog-to-digital converter (ADC) incorporates redundancy, reassignment, and digital correction to reduce the complexity of analog functions and the required accuracy compared to traditional Flash ADCs. Deliberate and random mismatch is used to set the desired trip points, achieving a 600-mVpp differential input signal range. The need for a low-impedance high-precision resistor reference ladder is eliminated, and comparator performance is decoupled from matching requirements, so that small and fast dynamic comparators can be used. New analysis discusses the optimum combination of random and deliberate comparator offset to achieve a target effective number of bits (ENOB). This prototype ADC has the highest ENOB and highest sampling frequency of any reported Flash ADC utilizing redundancy. A proof-of-concept prototype achieves no missing codes, 46.6-dB spurious-free dynamic range, and 6.05-bit ENOB at Nyquist input frequency. Fabricated in 90-nm digital CMOS, with a core area of 1.2 mm2, the device consumes 204 mW from a 1.2-V/0.9-V analog/digital supply.

Automated ADC characterisation using the histogram test stimulated by Gaussian noise

Abstract: A broadband variant of the histogram test where Gaussian noise is used as a stimulus signal is presented. A methodology allowing for an automated and extensive characterization of analog-to-digital converters (ADCs) is given. Tolerance and confidence intervals are determined both for the integral nonlinearity (INL) and differential nonlinearity (DNL) vectors, related to the number of samples acquired. Experimental results of the characterization of a VXI waveform digitizer using this methodology are shown.

Method and apparatus for micropower analog-to-digital conversion in an implantable medical device

Abstract: A micropower analog-to-digital converter (ADC) for use in an implantable medical device is disclosed. The ADC achieves a high conversion speed at micropower levels through a number of timing and circuit improvements over the conventional implementation of the successive approximation ADC architecture. The ADC includes a digital-to-analog converter (DAC) that preferably is implemented as a binary-weighted, switched capacitor array that employs top plate charging and performs bipolar conversion. The DAC provides an analog output signal representing array charge to a comparator. During a comparator latch phase, the DAC asynchronously determines a bit of the ADC digital output signal in response to the comparator output, and initiates a test of the next least significant bit during the same latch phase. Further, the DAC analog output signal is timed to settle during the latch phase in response to both the bit update and the next bit test. In conjunction with increasing conversion speed, the DAC reduces power requirements by using a power gated buffer that selectively increases the power of the ADC input signal only when necessary to drive the ADC conversion circuitry. Further, the comparator includes a precharged static memory cell to avoid crossover currents. Finally, the ADC includes a digital offset correction DAC that corrects not only the cumulative offset voltage generated by components of the ADC, but also the offset voltage of any device that provides the ADC input.