Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Successive approximation analog-to-digital converter with current steered digital-to-analog converter

Abstract: A successive approximation Analog-to-Digital Converter (“ADC”) having a successive approximation controller operably coupled to convert a control signal into a digital output of the successive approximation ADC, a current-steered Digital-to-Analog Converter operably coupled to convert the digital output of the successive approximation ADC into an analog feedback signal, and a comparator module operably coupled to compare the analog feedback signal with an analog input of the successive approximation ADC to produce the control signal. A further aspect is a method for increasing accuracy for a digital successive approximation of an analog input signal. The method includes determining a signal characteristic of the analog input signal to an Analog-to-Digital Converter (“ADC”), and selecting a reference voltage source of a Digital-to-Analog Converter of the ADC from a plurality of reference voltage sources based on the analog input signal.

When Are Low Resolution ADCs Energy Efficient in Massive MIMO

Abstract: Massive MIMO (MaMI) is often promoted as a technology that will enable the use of low-quality, cheap hardware. One particular component that has been in the focus of MaMI-related research is the analog-to-digital converter (ADC), and use of very low-resolution ADCs has been proposed. However, studies about whether this strategy is justified from an energy-efficiency point of view have largely been inconclusive. In this paper, we choose system setup and models that reflect the hardware implementation reality as close as possible and perform a parametric analysis of uplink energy efficiency as a function of ADC resolution. If antenna scaling and decrease of ADC resolution are considered independently, the energy efficiency is shown to be maximized at intermediate ADC resolutions, typically in the range of 4–8 bits. Moreover, optimal ADC resolution does not decrease when more antennas are used except in some specific cases, and when it does, the decrease is approximately logarithmic in the number of antennas. In the case when antenna scaling and ADC degradation are coupled through a constant-performance constraint, it is shown that energy efficiency cannot improve with reduced bit resolution unless the power consumption of blocks other than ADCs scales down with the upscaling of antennas at a fast enough rate. Altogether it is concluded that in MaMI, intermediate ADC resolutions are optimal in energy efficiency sense, and, except in some special cases, scaling up the antennas to very large numbers does not change this conclusion.

Why Analog-to-Information Converters Suffer in High-Bandwidth Sparse Signal Applications

Abstract: In applications where signal frequencies are high, but information bandwidths are low, analog-to-information converters (AICs) have been proposed as a potential solution to overcome the resolution and performance limitations of high-speed analog-to-digital converters (ADCs). However, the hardware implementation of such systems has yet to be evaluated. This paper aims to fill this gap, by evaluating the impact of circuit impairments on performance limitations and energy cost of AICs. We point out that although the AIC architecture facilitates slower ADCs, the signal encoding, typically realized with a mixer-like circuit, still occurs at the Nyquist frequency of the input to avoid aliasing. We illustrate that the jitter and aperture of this mixing stage limit the achievable AIC resolution. In order to do so, we designed an end-to-end system evaluation framework for examining these limitations, as well as the relative energy-efficiency of AICs versus high-speed ADCs across the resolution, receiver gain and signal sparsity. The evaluation shows that the currently proposed AICs have no performance benefits over high-speed ADCs. However, AICs enable 2-10X in energy savings in low to moderate resolution (ENOB), low gain applications.

A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC

Abstract: A 7-bit Nyquist folding and interpolating analog-to-digital converter (ADC) that converts at 300 MSamples/s is presented. Using current-mode signal processing techniques for analog preprocessing and a front-end sample-and-hold, the proposed 7-bit folding and interpolating ADC yields a wide input bandwidth up to 60 MHz with six effective number of bits. The ADC consumes 200 mW from a 3.3-V power supply. The chip occupies 1.2 mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.

A 2 nd order fully-passive noise-shaping SAR ADC with embedded passive gain

Abstract: An opamp-free solution to implement 2nd order noise shaping in a successive approximation register analog-to-digital converter is presented. This 2nd order fully-passive noise shaping, which has high power efficiency, is realized by charge-redistribution. A gain of 2 is required in this proposal which is realized by a passive method to save power. A prototype chip is fabricated in a 65-nm CMOS process occupying a core area of 0.0129 mm2. An ENOB of 10.5-bit is achieved at 64-MHz sampling frequency based on an 8-bit CDAC architecture when the OSR is 4. It dissipates 252.9 sW from a 1.0-V supply and achieves a Walden FoM of 10.9 fJ/conv.-step and a Schreier FoM of 169.9 dB.