Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

Abstract: This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control

Abstract: A 45nm CMOS 7b nonbinary 2b/cycle SAR ADC that operates up to 1GS/s with a 1.25V supply is presented. Use of a nonbinary decision scheme for decision error correction in a 2b/cycle structure not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuation and signal-dependent comparator offset variation. Proposed dynamic registers and a register-to-DAC direct control scheme enhance the conversion speed by minimizing logic delay in the decision loop. At a sampling rate of 1 GS/s, the chip achieves a peak SNDR of 41.6dB and maintains ENOB higher than 6b up to 1.3GHz signal frequency. The FoM is 80fJ/ conversion-step at 1GS/s with a power consumption of 7.2mW.

A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing

Abstract: In this paper, a 12-bit 1-kS/s successive approximation register analog-to-digital converter (ADC) is presented for biomedical signal processing system. A multi-segmentation digital-to-analog converter architecture and a hybrid switching scheme are proposed to reduce the total unit capacitor count. A new ultra low-leakage switch is proposed for sample-and-hold and capacitor control switch blocks in order to improve conversion accuracy and reduce leakage current. The proposed ADC is fabricated in 130-nm CMOS process with a core area of 0.16 mm2. The measurement results show that the ADC achieves 10.47 ENOB and consumes 110-nW power at a sampling rate of 1 kS/s with 1.0-V supply voltage. A Walden figure of merit of 76 fJ/conversion-step is obtained.

High-speed time interleaved ADCs

Abstract: Software-defined multi-gigahertz receivers require high-speed ADCs at the frontend. Time interleaving has emerged as the most common method of achieving ultra-fast quantization at reasonably high resolution. However, this multi-path solution introduces systematic errors due to mismatches in signal paths, whereas in non-interleaved versions these were mixed to DC, where they appeared as a harmless offset. Mitigating all possible time-interleaved errors comes at a heavy cost in complexity, risk, and power. Knowing which errors are most important and which can be neglected in any given application is essential for picking an appropriate architecture and calibration scheme. Guidelines for reducing errors lead to potentially different architecture choices. When the goal is to use the fewest slices, an inerleaved pipelined ADC results, whereas when the overriding objective is to use the simplest slice possible, a large array of SAR slices is usually adopted. Both approaches have merit. This article addresses when and where to use each approach by discussing specification requirements and showing that different types of error sources should not be merged into one single metric like ENOB, but should be treated separately to determine their impact on overall system performance. An example of an eight-way interleaved pipelined ADC is presented, which illustrates these principles in the context of a real circuit.

Communication Limits with Low Precision Analog-to-Digital Conversion at the Receiver

Abstract: We examine the Shannon limits of communication systems when the precision of the analog-to-digital conversion (ADC) at the receiver is constrained. ADC is costly and power- hungry at high speeds, hence ADC precision is expected to be a limiting factor in the performance of receivers which are heavily based on digital signal processing. In this paper, we consider transmission over an ideal discrete-time real baseband additive white Gaussian noise (AWGN) channel, and provide capacity results when the receiver ADC employs a small number of bits, generalizing our prior work on one bit ADC. We show that dithered ADC does not increase capacity, and hence restrict attention to deterministic quantizers. To compute the capacity, we use a dual formulation of the channel capacity problem, which is attractive due to the discrete nature of the output alphabet. The numerical results we obtain strongly support our conjecture that the optimal input distribution is discrete, and has at most one mass point in each quantizer interval. This implies, for example, that it is not possible to support large alphabets such as 64-QAM using 2-bit quantization on the I and Q channels, at least with symbol rate sampling.