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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


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Journal ArticleDOI
TL;DR: A trilevel switching scheme with common-mode reset, redundant algorithm, and a time-domain comparator is proposed and implemented to achieve ultralow power consumption.
Abstract: As the low-power-consumption requirement of integrated circuits for biomedical applications (e.g., wearable sensor nodes operating with and without batteries, and implantable medical devices powered by batteries and wireless charging) becomes more stringent, the data converter design evolves toward mircrowatt and submircrowatt power consumption. In this brief, a 400-nW successive approximation analog-to-digital converter (SAR ADC) is presented. A trilevel switching scheme with common-mode reset, redundant algorithm, and a time-domain comparator is proposed and implemented to achieve ultralow power consumption. The redundant algorithm mitigates the offset error caused by the level mismatch of the trilevel switching scheme, whereas the trilevel switching scheme simplifies the switching logic of the redundant algorithm. Fabricated in a 0.18-μm CMOS process, the proposed SAR ADC achieves a signal-to-noise-and-distortion ratio of 50 dB, which is equivalent to an 8-bit effective number of bits, at an 80-kS/s conversion rate. The figure of merit is 19.5 fJ/conversion step.

37 citations

Patent
25 Feb 2005
TL;DR: In this paper, the transmitter and receiver share information on the maximum number of bits communicated per symbol in a radio communication system, where the transmitter station allocates the bits from the codeword to each symbol, and the receiver station demodulates the symbols using a modulation type which processes symbols having a number equal to or smaller than the maximum bit per symbol.
Abstract: In a radio communication system, transmitter and receiver stations share information on a maximum number of bits communicated per symbol. The transmitter station encodes a signal with sufficient error correcting capabilities to create a codeword. The transmitter station allocates the bits from the codeword to each symbol, modulates the symbols using a modulation type which processes symbols each having a number of bits equal to or smaller than the maximum number of bits per symbol, and transmits the modulated symbols. The receiver station demodulates the symbols using a modulation type which processes a larger number of bits per symbol as the transmission path quality is higher from among modulation types which process symbols having a number of bits equal to or smaller than the maximum number of bits per symbol.

37 citations

Journal ArticleDOI
TL;DR: Model techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs) are presented and design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications.
Abstract: We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.

37 citations

Patent
Paul J. Cooper1
22 Dec 1976
TL;DR: In this paper, a method for increasing the output data per unit time from a computer to its associated peripheral terminals or utilization devices is disclosed in which the computer output address and data lines are time multiplexed by a novel decoding technique which enables the address bits and data bits to be interpreted together to form a new data word having a number of bits equal to the sum of the original data bits and the addresses interpreted as data bits.
Abstract: A circuit and method for increasing the output data per unit time from a computer to its associated peripheral terminals or utilization devices is disclosed in which the computer output address and data lines are time multiplexed by a novel decoding technique which enables the address bits and data bits to be interpreted together to form a new data word having a number of bits equal to the sum of the original data bits and the address bits interpreted as data bits. A plurality of decoders, each at a peripheral terminal and each having an identification address code, enable a window for decoding multiple transfers of data on output address and data lines, said window having a predetermined time duration during which all other peripheral identification address codes are locked out, until the data transfer is completed. A microprocessor embodying the invention is also disclosed in which the output data capability is increased from eight to sixteen bits without hardware modification to the microprocessor.

36 citations

Proceedings ArticleDOI
25 Feb 2016
TL;DR: The reported ADC demonstrates a digital timing-skew correction technique incorporated with a delta-sampling technique, and achieves a 2.6GHz sampling rate and a wide signal bandwidth.
Abstract: Recent radio architectures, such as WiGig and 5G, require ADCs with bandwidth beyond 1GHz and ENOB of 6-to-8b while retaining excellent power efficiency for long battery life. Therefore, many time-interleaved SAR ADCs are used in a distributed sampling scheme, leaving the timing-skew problem to be resolved by calibration. Only a few timing-skew calibration algorithms have been reported for interleaved ADCs to correct timing error in the analog domain [1,2] or in the digital domain [3]. The drawback of analog correction includes the feedback-induced stability hazard and jitter introduced by the controlled delay line. Digital-domain correction takes advantage of technology scaling but the complex slope-extraction filter limits signal bandwidth. The reported ADC demonstrates a digital timing-skew correction technique incorporated with a delta-sampling technique, and achieves a 2.6GHz sampling rate and a wide signal bandwidth.

36 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147