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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


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Patent
21 May 1990
TL;DR: In this paper, a hardware implementation of an algorithm for a run length limited (1,7) block code of rate 2/3, wherein 2 unconstrained bits are mapped onto 3 constrained bits, was presented.
Abstract: The present invention comprises the hardware implementation of an algorithm for a run length limited (1,7) block code of rate 2/3, wherein 2 unconstrained bits are mapped onto 3 constrained bits. The encoded data stream has a minimum of 1 "zero" between adjacent "ones", and a maximum of seven "zeros" between adjacent "ones". Unlike earlier (1,7) block encoders, the encoder of the present invention is a 4 state machine whose internal state description requires only 2 bits, rather than the 3 bits as taught in the prior art. The 4 state encoder combines the 2 incoming data bits with present state information to generate the output encoded sequence, and the next state designation. Error propagation due to a single channel bit error is limited to 5 bits. The decoder of the invention utilizes three, 3 bit shift registers which hold 9 bits of the encoded data; each group of three bits is decoded into 2 bits corresponding to the original input bits by means of a logic array fed from the three shift registers.

36 citations

Journal ArticleDOI
TL;DR: A 5 V single supply, 6-bit flash A/D converter (ADC) has been developed that supports sampling rates of up to 80 Ms/s and is optimized to operate in undersampling applications where the ADC has to deliver greater than 5.2 Effective Number of Bits (ENOB's) with input frequencies well beyond Nyquist.
Abstract: A 5 V single supply, 6-bit flash A/D converter (ADC) has been developed that supports sampling rates of up to 80 Ms/s. The converter is optimized to operate in undersampling applications where the ADC has to deliver greater than 5.2 Effective Number Of Bits (ENOB's) with input frequencies well beyond Nyquist. Excellent dynamic linearity performance has been achieved with input frequencies up to 75 MHz and a gain flatness of better than 0.1 dB is obtained over the input signal spectrum of 50 MHz-95 MHz. This ADC is fabricated on a 1.0 /spl mu/m advanced BiCMOS process that features trench-isolated bipolar devices with an f/sub t/ of 10 GHz. >

36 citations

Journal ArticleDOI
TL;DR: This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital- to-analog converter (CDAC) that exhibits a 95% reduction in switching energy, a 50% reduced in capacitor area, and with 30% reduction of nonlinearity under the same unit capacitor size and matching condition.
Abstract: This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 $\mu{\rm m}$ CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 $\mu{\rm W}$ from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus- distortion ratio is 54.6 dB $({\rm ENOB}=8.8)$ at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size.

36 citations

Patent
19 May 2000
TL;DR: In this paper, a bit detect unit detects the condition of a pre-determined number of bits of an operand and initiates an operation packing signal when common operations are ready to issue.
Abstract: Circuitry reduces power consumption by a microprocessor with operand-value-based clock gating. A bit detect unit detects the condition of a pre-determined number of bits of an operand. If the pre-determined number of bits are not necessary for executing the operand, a condition detect signal is generated. Gating logic receives the condition detect signal and initiates a gated clock signal. Latching circuitry or pre-charge circuitry receives the gated clock signal and disables the pre-determined number of bits, preventing the execution of unnecessary bits by the microprocessor and reducing the power consumed during execution. Operation packing improves microprocessor performance by packing narrow-width operations for parallel execution by the microprocessor. A bit detect unit detects the condition of a pre-determined number of bits of an operand and initiates a condition detect signal. Issue logic detects common operations within execution instructions and receives the condition detect signal, initiating an operation packing signal when common operations are ready to issue and the operands involved contain a pre-determined number of bits unnecessary for execution. Multiplexers receive the operation packing signal and move data from the lowermost bits of the operands to the upper sub-words of the source operand bus, creating a parallel sub-word operation. After execution, multiplexers move data from upper sub-words of the result onto the lowermost bit boundaries of the individual result operands.

36 citations

Proceedings ArticleDOI
01 Jun 2014
TL;DR: In this paper, an S-band RF I/Q power DAC transmitter with embedded mixed-domain finite-impulse-response (FIR) filter is presented to suppress out-of-band quantization noise for FDD/co-existence.
Abstract: This paper presents an S-band RF I/Q power DAC transmitter with embedded mixed-domain finite-impulse-response (FIR) filter to suppress out-of-band (OOB) quantization noise for FDD/co-existence. Watt-level output power and low output OOB noise level is achieved through (1) power combining (2) device stacking with thick oxide devices in a switching-class power amplifier (PA) and (3) embedded RF FIR filtering. To combat the strong conductance-to-amplitude/phase nonlinearity of switching-class digital PAs, a transformer-based FIR architecture is proposed that ensures completion of filtering after the nonlinearity. Implemented in 65 nm CMOS, the transmitter has a measured peak output power of 29.1 dBm with 42% system efficiency at 2.25 GHz. The measured noise floor at 100 MHz offset from the 2.4 GHz carrier is -134 dBc/Hz for a 20 MHz 64-QAM signal at 200 MSa/s including 8 dB noise floor suppression from transformer-based two-tap third-order FIR filtering, yielding an ENOB of 8.18.

36 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147