Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Semiconductor memory device with an on-chip error correction circuit and a method for correcting a data error therein

Abstract: Disclosed is semiconductor memory device and a method for correcting a data error therein. The device comprises a memory cell array that stores a plurality of data bits and a plurality of check bits corresponding to the plurality of data bits. A read circuit is further provided that performs an operation of reading out the plurality of data bits and the plurality of check bits from the memory cell array. The semiconductor memory device further comprises error circuits for correcting a first error in the data bits of the first group and a second error in the data bits of the second group, respectively. The error circuit receives in parallel odd-numbered and even-numbered data and check bits read out from the memory cell array during a first cycle of a read mode of operation and generates first syndrome bits and second syndrome bits. During a second cycle of the read mode of operation, the circuit corrects the error in the odd-numbered data bits and the error in the even-numbered data bits responsive to the first and the second syndrome bits, respectively.

A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS

Abstract: This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 $\mu\mbox{W}$ and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm 2.

A 0.47–1.6 mW 5-bit 0.5–1 GS/s Time-Interleaved SAR ADC for Low-Power UWB Radios

Abstract: This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400 aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90 nm CMOS occupies only 0.11 mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5 GS/s at 0.75 V supply, and 1 GS/s at 1 V supply with 0.47 mW and 1.6 mW power consumption respectively. With an ENOB of 4.7 and 4.8 bits, this leads to energy efficiencies of 36 and 57 fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

DAC-based optical modulator and demodulator

Abstract: Methods, systems, and devices are described for modulating and demodulating data on optical signals. During modulation, at least one stream of symbol mapped bits is filtered with at least one pulse shaping filter to reduce a bandwidth of the stream of bits and to pre-compensate for at least one identified non-ideal transmission condition. The filtered bits are modulated onto a waveform in the digital domain, and the modulated filtered bits are transmitted to digital-to-analog converter. The output of the digital-to-analog converter is converted to an optical signal. During demodulation, a received optical signal is sampled at a first sampling rate at an ADC, downsampled to a lower sampling rate for filtering, filtered with at least one discrete pulse-shaping filter, upsampled for equalization and demodulation, and then equalized and demodulated.

Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS

Abstract: This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2/sup nd/ order noiseshaped. It is implemented in a 0.13 /spl mu/m standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.