Topic
Effective number of bits
About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.
Papers published on a yearly basis
Papers
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TL;DR: By using additional decimation filtering of the ADC output at room temperature, its dynamic programmability and resolution-bandwidth tradeoff was demonstrated and the measured ADC performance was competitive with the best semiconductor high-resolution ADCs.
Abstract: We report successful demonstration of a fully operational integrated superconducting ADC system based on a phase modulation/demodulation architecture. It consists of a high-resolution ADC chip with a multiple-channel race arbiter and integrated bit-pipelined decimation filter, an interface electronics block converting the ADC output to standard ECL form at sampling rates up to 200 MHz, and a computerized test station performing data acquisition, processing and display in real time. We have demonstrated a fully functional 14-bit ADC chip with 2-channel race arbiter and 16-bit decimation filter with 1:64 decimation ratio operating at 11.2 GS/s. By using additional decimation filtering of the ADC output at room temperature we demonstrated its dynamic programmability and resolution-bandwidth tradeoff. The measured ADC performance (on effective bits) was competitive with the best semiconductor high-resolution ADCs.
33 citations
05 Jan 2009
TL;DR: A low power and variable resolution (adaptive) flash ADC that enables exponential power reduction while the reduction in resolution is linear is proposed.
Abstract: In this paper, a low power and variable resolution (adaptive) flash ADC is proposed. The ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design, unused parallel voltage comparators are switched to standby mode leading to consumption of only the leakage power. The ADC, capable of operating at 4-bit, 5-bit, and 6-bit precision, dissipates 6mW at 4-bit and 12mW at 6-bit, and operates at a sampling frequency of 1 to 2 GSPS. The ADC has been designed and simulated in standard 65nm CMOS technology using Cadence tools
33 citations
Patent•
29 May 1984TL;DR: In this paper, a method and apparatus for recording and reading information in the form of a track of pit and land areas on an optical digital disc record carrier is described, where the information is first encoded from symbol blocks of data bits into symbol block of channel bits to which are added merging bits selected so as to minimize the d.c. unbalance or digital sum value of the channel bits.
Abstract: A method and apparatus for recording and reading information in the form of a track of pit and land areas on an optical digital disc record carrier. The information is first encoded from symbol blocks of data bits into symbol blocks of channel bits to which are added merging bits selected so as to minimize the d.c. unbalance or digital sum value of the channel bits. Those parts of the stream of channel bits for which the d.c. unbalance does not meet predetermined criteria are subjected to selective scrambling to correct such unbalance prior to recording. During read-out the correctively scrambled parts of the recovered symbol blocks of data bits are descrambled in an inverse manner. Information identifying such parts is recorded with the channel bits. The invention also relates to a record carrier on which information has been so recorded.
33 citations
Patent•
NEC1
TL;DR: In this article, a driving circuit of a display device including a TFT (Thin Film Transistor) liquid crystal display device or the like is provided which is capable of decreasing a chip in size and reducing costs of testing by reducing the number of bits.
Abstract: A driving circuit of a display device including a TFT (Thin Film Transistor) liquid crystal display device or the like is provided which is capable of decreasing a chip in size and reducing costs of testing by reducing the number of bits even in the case of increased number of bits of digital image data to perform multi-gray shade displaying. The driving circuit of the display device has a gray shade voltage generating circuit adapted to generate a plurality of voltages, gray shade voltage selecting circuits used to select one voltage out of a plurality of voltages supplied from the gray shade voltage generating circuit based on high order bits composed of one or two and more bits counted from the most significant bit of the digital image data and the number of bits of which is smaller than that of the digital image data and to output it, operational amplifiers used to convert an impedance of a voltage outputted from gray shade voltage selecting circuits and voltage adjusting circuits used to induce a voltage rise or a voltage drop in voltages outputted from the operational amplifier based on low order bit of the digital image data excluding its high order bits.
33 citations
TL;DR: An 8-bit 15MS/s A/D converter using a differential Switched-Current (SI) pipeline architecture is described, noteworthy in being optimised so that the converter maintains performance across the whole input Nyquist band.
Abstract: This paper describes the architecture and circuit design of an experimental 8-b differential 15 MS/s CMOS A/D converter, implemented using the switched-current (SI) technique. Particular emphasis has been given to maintaining analog bandwidth and hence the effective number of bits right across the input Nyquist band. Individual cells have also been optimized for inherent accuracy to achieve good performance in a simple uncorrected conversion algorithm. The converter is fabricated in a standard 0.8 /spl mu/m 5 V digital CMOS process and occupies 2.4 mm/sup 2/.
33 citations