Topic
Effective number of bits
About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.
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23 May 2005
TL;DR: A 4-bit 5 GS/s flash analog-to-digital converter (ADC) designed and simulated in a 0.18 /spl mu/m CMOS technology demonstrates a significant improvement in terms of power and area compared to those of previously reported ADCs.
Abstract: A 4-bit 5 GS/s flash analog-to-digital converter (ADC) is designed and simulated in a 0.18 /spl mu/m CMOS technology. Low-swing operation both in the analog and the digital circuitry results in high-speed low power operation. The ADC dissipates 70 mW power from a 1.8 V supply while operating at 5 GHz. Offset averaging is used to minimize the effect of comparator offsets. Simulation results show that offset voltages with 67 mV standard deviation (i.e., 1 LSB) can be tolerated. Static INL and DNL errors are 0.34 LSB and 0.24 LSB respectively, and the ENOB is 3.65 bits. The simulation results of this non-time-interleaved flash ADC demonstrates a significant improvement in terms of power and area compared to those of previously reported ADCs.
33 citations
Patent•
11 Feb 1999TL;DR: In this paper, a digital input PWM power amplifier includes an oversampling and noise shaping circuit receiving PCM digital input data organized in words of a first number of M bits at a bit rate, and outputting PWM digital data organized with a smaller number of N bits at multiple bit rate.
Abstract: A digital input PWM power amplifier includes an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number of M bits at a bit rate, and outputting PCM digital data organized in words of a smaller number of N bits at a multiple bit rate. A first bus transmits a first number of most significant bits (MSB) of the N bit words output from the oversampling and noise shaping circuit, and a second bus transmits a second number of least significant bits (LSB) of the N bit words output from the oversampling and noise shaping circuit. First and second PCM/PWM converters are respectively fed with the first and second number of bits transmitted through the first and second buses. The PWM signal output by the first converter is summed to an attenuated PWM signal output by the second converter on the inverting input node of the output power stage.
33 citations
Patent•
21 Apr 1986TL;DR: In this paper, a serial-to-parallel and parallel-to serial data format converter has a plurality of first-in-first-out (FIFO) buffer memory devices, an input circuit for receiving serial data bits, an output circuit for outputting serial data bit and a clocking circuit for clocking selected ones of the data bits into and out of selected ones.
Abstract: A serial-to-parallel and parallel-to-serial data format converter has a plurality of first-in, first-out (FIFO) buffer memory devices, an input circuit for receiving serial data bits, an output circuit for outputting serial data bits and a clocking circuit for clocking selected ones of the data bits into and out of selected ones of the FIFO buffer memory devices. The clocking circuit clocks serial data bits either into or out of each of the FIFO buffer memory devices at a rate slower than the rate of the receipt of the serial data bits by the input circuit, or the rate of the outputting of serial data bits by the output circuit, respectively.
33 citations
TL;DR: It is shown that the intelligent CADC (ICADC) built on this principle most efficiently utilise the resources of their analogue and digital parts, and their performance may achieve theoretically available upper boundaries.
33 citations
Patent•
07 Aug 2003
TL;DR: A random number generator comprises interface circuitry to receive and store random bits output by the random number generation circuitry and to output random bits as discussed by the authors, which prevents outputting the same random bits more than once.
Abstract: A random number generator comprises random number generation circuitry to generate and output random bits. The random number generator comprises interface circuitry to receive and store random bits output by the random number generation circuitry and to output random bits. The interface circuitry prevents outputting the same random bits more than once.
33 citations