Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

Method for reducing DAC resolution in multi-bit sigma delta analog-to digital converter (ADC)

Abstract: A method for reducing the resolution of a digital-to-analog converter in a multi-bit sigma-delta ADC is described. With the addition of digital sigma-delta modulators in the feedback path of a sigma-delta ADC, the truncation errors between the digital word output of the multi-bit sigma-delta ADC to the DAC input can be shaped to higher order than that of the quantization error. Thus, the DAC resolution can be reduced and the implementation of DEM for multi-bit DAC can be avoided. A preferred embodiment comprises selecting an outermost feedback loop in a sigma-delta ADC that has not been replaced and replacing it with a circuit with an equivalent transfer function. The circuit can be further enhanced with an additional term if the order of the noise shaping of the circuit is less than the order of the noise shaping of the sigma-delta ADC.

Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs

Abstract: Digital correction and calibration techniques have been extensively used to cancel linear circuit imperfections in pipelined analog-to-digital converters (ADCs). The self-calibration technique proposed in this paper provides a means of measuring and canceling nonlinear errors of interstage amplifiers in the digital domain. The calibration of nonlinearity coefficients is based on pseudorandom signal modulation and evaluation of digital code histograms. The scheme does not introduce additional precision hardware or test signals and operates in the background without interrupting normal converter operation. The simulation results of a 12-bit ADC show that the calibration is capable of improving the effective number of bits from 7 to 11.8 while achieving parameter adaptation time constants on the order of 100 ms at a sampling rate of 100 MS/s.

Large range, high speed, high accuracy digital-to-analog converter.

Abstract: A digital-to-analog converter system includes a logic system which receives input signals, receives an increment/decrement signal, and provides a digital word composed of most significant bits and least significant bits. The system includes two DACs haaving separate data rates and ranges for converting the most significant bits and the least significant bits, respectively, the data rate of the second DAC being greater than the data rate of the first DAC. Combining circuitry produces an analog signal representative of the digital word from the first and second analog outputs. The data rate of the combined output may be as fast as the data rate of the second DAC, and the range of the combined output may be as large as the range of the first DAC. The system also includes track and hold circuitry which holds the value of the output of the first DAC until glitches are settled.

A Time-Domain High-Order MASH $\Delta\Sigma$ ADC Using Voltage-Controlled Gated-Ring Oscillator

Abstract: In this paper, a time-domain high-order ΔΣ analog-to-digital converter (ADC) using voltage-controlled gated-ring oscillator (VC-GRO) and time-domain multi-stage-noise-shaping (MASH) is introduced. To implement the high-order noise transfer function (NTF), a voltage-controlled oscillator (VCO) and VC-GRO quantizers are cascaded. Unlike conventional high-order ΔΣ ADC using feedback loop, the proposed ADC has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process. The performance of the proposed ADC is theoretically analyzed and simulated, including non-ideal conditions such as nonlinearity, mismatch, propagation delay of logic gates, phase noise, and sampling clock jitter.

High-speed computation in arithmetic logic circuit

Abstract: An arithmetic computation circuit is implemented to significantly increase throughput and thereby permit processing of relatively large binary numbers in a relatively small period of time. In one embodiment, the arithmetic computation circuit adapted to add a first binary operand of N bits and a second binary operand of M bits, where N is greater than or equal to M. The circuit includes an adder and a multiplexer circuit. The adder is adapted to combine representative sets of least-significant bits of the first and second binary operands together to produce a least-significant bits partial sum and a carryout. The multiplexer circuit is adapted to output a most-significant bits partial sum by passing one of: a representative set of most-significant bits of the first binary operand, and an offset of the representative set of most-significant bits of the first binary operand; the selection of these inputs is responsive to selection data that is a function of the most-significant bit of the representative set of least-significant bits of the first binary operand.