Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

DRAM compressed data test mode with expected data

Abstract: A unique method of testing an integrated circuit DRAM for incorrect stored data is disclosed. A JEDEC test mode entry is initiated by normal means, i.e., Write Enable (WE*) and Column Address Select (CAS*) before Row Address Select (RAS*) with specific address data to select a specific test. Data bits are then loaded in the DRAM cells and column data bits compared. The subarray bits are also compared with bits in an expected data register which has been loaded at the beginning of the read cycle. If column bits match and subarray bits match the expected data register, ones are indicated on the data (out) bus; otherwise, a zero appears in case of a data error.

Two-step switched-capacitor digital to analog converter

Abstract: In accordance with the present invention, the circuitry of the ten bit switched capacitor digital to analog converter utilizes five binary weighted input capacitors and a digital circuit to perform multiplexing and generating the necessary timing. A combination of input capacitors and feedback capacitors give rise to an output voltage in an amount proportional to digital input bits in a binary fashion such that in the first step, the output voltage is proportional to the first five least significant bits divided by 32 and the second step the output voltage would be equal to the previous value plus a voltage proportional to the five most significant bits. Therefore, at the end of the second step, the output voltage is an analog voltage proportional to the binary input bits times the reference voltage divided by 1024.

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC

Abstract: A complementary dynamic single-stage residue amplifier for a pipelined SAR ADC is presented. It re-uses charge typically wasted during the reset phase, and hence improves efficiency by a factor 2× in this block that often dominates the fundamental noise/power trade-off of the ADC. The residue amplifier achieves 90 µVrms input noise for an energy consumption of 1.5 pJ. It is used in a 2-times interleaved 6b coarse/8b fine pipelined SAR ADC. The 40nm CMOS prototype achieves 11 ENOB at 20 MS/s while consuming 165 µW, leading to an energy per conversion step of 4 fJ. It maintains more than 10.8 ENOB at low input frequencies for a clock frequency up to 180 MS/s.

A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators

Abstract: The design and wafer probe test results of a 5-bit SiGe flash ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with dual Nyquist operation at sample frequencies up to 20 GHz. Sampling clock rates are demonstrated as high as 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease data capture with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low-frequency input tones, dropping to 4.0 at 10 GHz.

Frequency Dependent ENoB Requirements for M-QAM Optical Links: An Analysis Using an Improved Digital to Analog Converter Model

Abstract: Digital-to-Analog Converters (DACs) are a key technology for high-speed optical links and are widely deployed. A new and improved model for a DAC that accurately accounts for the frequency dependent nature of ENoB and is computationally efficient is validated through both simulations and experiments. Furthermore, the impact of the various model parameters such as quantization, timing jitter and bandwidth, on the performance of 16QAM, 64QAM, and 256QAM are presented.