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Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.


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Journal ArticleDOI
TL;DR: In this article, the response of a pipelined analog-to-digital converter (ADC) to radiation-induced single-event transients is evaluated using circuit simulations.
Abstract: Circuit simulations are used to determine the response of a pipelined analog-to-digital converter (ADC) to radiation-induced single-event transients. The ADC uses a cascade of 9 stages which each resolve 1.5 bits. Digital error correction is used to reassemble the bits and to correct for errors in the comparators and sub-DAC. A Monte-Carlo methodology is used to simulate the single-event vulnerability of the circuit. Circuit simulations are performed using the Spectre circuit simulator. Sensitive cross-sections were derived from an analysis of the simulation results. Sensitive areas were identified and hardening techniques were applied to the circuit. These techniques may be applicable to other mixed-signal and switched-capacitor circuits. A significant reduction in the sensitive cross-section was obtained by application of these hardening techniques

29 citations

Journal ArticleDOI
TL;DR: The design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter in 28-nm low-power digital CMOS shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations.
Abstract: This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of ${\hbox{0.12 mm}}^{2}$ . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.

29 citations

Proceedings ArticleDOI
08 Aug 2000
TL;DR: An internally analog, externally digital architecture for matrix-vector multiplication is presented, which allows for high data throughput and minimal latency, and is tailored for high-density and low power VLSI implementation.
Abstract: An internally analog, externally digital architecture for matrix-vector multiplication is presented. Fully parallel processing allows for high data throughput and minimal latency. The analog architecture incorporates an array of charge-mode analog computational cells with dynamic storage and row-parallel flash analog-to-digital converters (ADC). Each of the cells includes a dynamic storage element and a charge injection device computing binary inner product of two arguments. The matrix elements are stored in the array of computational cells in bit-parallel fashion, and the input vector is presented bit-serially. Digital post-processing is then performed on the ADC outputs to construct the resulting product with precision higher than that of each conversion. The analog architecture is tailored for high-density and low power VLSI implementation, and matrix dimensions of 128/spl times/512 and ADC resolution of 6 bits for an overall resolution in excess of 8 bits are feasible on a 3 mm/spl times/3 mm chip in standard CMOS 0.5 /spl mu/m technology.

29 citations

Proceedings ArticleDOI
31 Aug 2005
TL;DR: It is shown that various forms of the standard variance of time jitter are convergent in the presence of 1/fn noise, if one explicitly considers the properties of the system phase response function for each of these categories.
Abstract: Time jitter is an important parameter for determining the performance of digital systems. This paper reviews how time jitter impacts the performance of digital systems. For the purposes of later discussions, digital systems are broken down into three major categories: synchronous data transfer, asynchronous data transfer, and digital sampling systems. A statistical framework is first developed for treating time jitter. This framework explicitly deals with issues of bandwidth and noise processes with 1/fn spectra. It is shown that various forms of the standard variance of time jitter are convergent in the presence of 1/fn noise, if one explicitly considers the properties of the system phase response function for each of these categories. It is also shown that standard variances are preferred over 2nd difference variances in dealing with digital performance issues such as bit errors, because standard variances can be directly related to the total time error (jitter plus skew). Detailed discussions of how time jitter impacts the enumerated categories of digital systems are then presented. In synchronous data transfer systems, it is shown that time jitter causes hard bit errors, that only the white noise components of clock oscillator and gate noise make appreciable contributions to the time jitter, and that aliasing of this white noise is a major issue. In asynchronous systems, it is shown that time jitter can also cause soft errors or bit error rate degradation and that there is an additional time jitter term due to relative master clock-local clock oscillator jitter, whose value is determined by 1/f n oscillator noise as well as the white noise. Finally, for digital sampling in analog-to-digital and digital-to-analog converters, it is shown that noise power or multiplicative decorrelation noise generated by sampling clock jitter is a major limitation on the bit resolution (effective number of bits) of these devices

29 citations

Patent
28 Dec 1993
TL;DR: In the case where a multiplier factor is a constant, if the bits having the value of 1 in the multiplier factor are 3 or more and if it is larger than the number of the bits with the value 0, a circuit for performing multiplication by using the logic not number of multiplier factor, which is obtained by inverting all the bits in the multiplicative factor by the logic NOT operation is generated as discussed by the authors.
Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.

29 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202361
2022143
202196
2020147
2019149
2018147