Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

High efficiency technique for coding a digital video signal

Abstract: The invention relates to a high efficiency apparatus for coding digital video data in which the number of bits per picture element in the video data such as a digital video signal or the like is compressed. The video data of a television picture plane is divided into a number of three-dimensional blocks, i.e., spatial blocks. The picture element data in the block can be coded by the reduced number of bits by the bit compression by performing the coding process adapted to the narrowed dynamic range on the basis of the correlation among the picture elements in each block. The transmission data of the number of bits reduced as compared with the number of bits of the original data can be formed. By coding only the necessary frame by discriminating the movement of the image in the block, the redundancy in the direction of time can be removed.

An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications

Abstract: An adaptive resolution (AR) asynchronous analog-to-digital converter (ADC) architecture is presented. Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. An AR algorithm automatically varies the ADC quantizer resolution based on the rate of change of the input. This overcomes the trade-off between dynamic range and input bandwidth typically seen in asynchronous ADCs. A prototype ADC fabricated in a 0.18 μm CMOS technology, and utilizing the subthreshold region of operation, achieves an equivalent maximum sampling rate of 50 kS/s, an SNDR of 43.2 dB, and consumes 25 μW from a 0.7 V supply. The ADC is also shown to provide data compression for accelerometer applications as a proof of concept demonstration.

Multi-channel parallel/serial concatenated convolutional codes and trellis coded modulation encoder/decoder

Abstract: A method and apparatus to transmit turbo-encoded data in a multitone channel assigns the original data and selected parity bits across multitone subchannels allowing transmission of an entire turbo-encoded block withing one or few symbol time frame. Parity bits are selected by a procedure using data derived by optimization using simulation of a single-channel system. The optimization determines, for a specified bit error rate, for each possible number of information bits per symbol, the code rate corresponding to the lowest signal-to-noise ratio. Alternatively, in the simulation non-identical integer values may be applied to the channels to approximate non-integer values of code rate and information bits-per-channel in the aggregate. The optimized data are used to determine an optimal code rate and SNR for each channel. In assigning the respective bits to the channels, the number of parity bits in each channel are shared.

Digital-to-analog converter having high resolution and high bandwidth

Abstract: A digital-to-analog converter (DAC) is preferably employed to receive a digital input word and provide an analog output signal to a motor driver in a disk drive servo. The digital input word has a plurality of bit positions for establishing a resolution for the DAC. These bit positions define first and second groups of bits. The DAC comprises circuitry responsive to the first group of bits for producing a pair of analog signals defining a common-mode magnitude and a differential magnitude. The common-mode magnitude is a function of the value of the first set of bits and the differential magnitude is a function of the number of bit positions in the first group of bits. In the DAC: a clock generates a clocking signal; a state machine has an input for receiving the clocking signal, an input for receiving the second groups of bits, and an output for providing a time-varying control signal; switching circuitry has a pair of inputs for receiving the pair of analog signals, an input for receiving the time-varying control signal, and an output for providing a pulse-width and amplitude modulated signal; and averaging circuitry responds to the pulse-width and amplitude modulated signal to producing the analog output signal.

An 8-b 650-MHz folding ADC

Abstract: Where a flash analog-to-digital converter (ADC) needs 2/sup N/-1 comparators to convert an analog value into an N-bit binary code, an M-times folding ADC can perform this function needing slightly more than 2/sup N//M comparators. In the design reported, N=8 and the folding factor M=8. Reduction in the number of comparators is obtained by analog preprocessing of the ADC input signal. In the design considered, power consumption, chip area, and parasitic capacitance at the analog input of the ADC are reduced by using only four folding blocks and 8-times interpolation. >