Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS

Abstract: A 10b 160MS/S subranging ADC with THA is implemented in a 90nm digital CMOS process. Noise averaging and an auto-zeroed comparator are used in the fine converter to achieve low noise and offset at low power dissipation. The prototype converter achieves an ENOB of 9.1b for an 80MHz input and consumes 84mW from a 1V supply

Estimation circuit for time-interleaved adc and method thereof

Abstract: The present invention provides an apparatus and a method for estimating at least one of timing, gain, and offset errors of a time-interleaved ADC. The apparatus has a first ADC, a second ADC, a converter, an estimator, and a compensator. The converter has a Fourier Transform converter and a calculator.

Carrier-dependent dithering for analog-to-digital conversion

Abstract: An analog-to-digital converter (100) (ADC) includes a dither signal generator (107) configured to add an analog dither signal (114) to the analog input signal (102) of the ADC prior to digitization (i.e., quantization). The amplitude of the either signal is selected based upon the power levels of one or more carriers present in the bandwidth for which the ADC is designed to operate. Addition of the dither signal to the input signal in the analog domain reduces quantization noise such as conversion spurs that result from non-linearities in the ADC transfer function.

Computationally efficient convolutional coding with rate-matching

Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate

A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN

Abstract: A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets $WiGig$ standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a “correct-by-construction,” timing-calibration-free global bottom-plate sampling scheme. The ADC achieves a sampling rate of 2.64 GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40 nm LP CMOS design dissipates 39 mW from 1.2 V. The TI-SAR ADC characterized with an integrated receiver front-end achieves $-$ 21.44 dB EVM at sensitivity with a QAM16 signal.