Effective number of bits

About: Effective number of bits is a research topic. Over the lifetime, 3776 publications have been published within this topic receiving 46130 citations.

A 5-bit 1-GS/s Flash-ADC in 0.13-μm CMOS Using Active Interpolation

Abstract: This work presents a 5-bit 1-GS/s flash-ADC in 0.13-μm CMOS technology. An active interpolation topology is used in the comparator inputs to reduce power consumption and input capacitance of the converter. Operating at 1.056-GS/s the ADC consumes 46 mW of power from a 1.2 V supply and provides an ENOB of 4.73 bits and an SFDR of 43.2 dBc at a signal frequency of 102 MHz. The ADC has an ERBW of 470 MHz and a FoM of 1.8 pJ/convstep. Area consumption for the converter is 0.2 mm2.

Highly parallel pulsed optoelectronic analog-digital converter

Abstract: We characterize the performance of a highly parallel pulsed optoelectronic analog to digital converter. The system is based on a time-domain to wavelength-domain mapping, such that an input analog signal is parallelized using a wavelength-division-demultiplexed scheme. Each parallel wavelength channel is then digitized using conventional, slow electronic analog-digital converters. We use narrow-band signals up to 18 GHz and histogram testing to characterize the system. From the measurements, we deduce the effective number of bits of the system to be /spl sim/6 and /spl sim/5 bits for 4 and 36 giga-samples-per-second (GSPS) sampling rates, respectively.

A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS

Abstract: This paper presents a 2b/cycle hybrid successive­approximation-register (SAR) analog-to-digital-converter (ADC) architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, the proposed ADC can generate 3 comparison levels needed for 2b/cycle without requiring extra DAC arrays. Eliminating extra DAC arrays reduces hardware cost, area, and power. The proposed SAR ADC takes advantage of 1b/cycle conversion mode and sufficient redundancy to address problems of multi-bit/cycle conversions, such as unmatched comparator offsets, kickback noise, and comparator input CM voltage variation. Reconfiguration to 1b/cycle is easily done by disabling the unneeded comparators for 1b/cycle conversion. A 10b prototype ADC is fabricated in 40nm LP CMOS process. It achieves peak 8.5b ENOB at sampling frequency of 300MS/s and consumes 2.1mW, leading to a FoM of 19.3fJ/conv-step.

On Dynamic Range of Digital Receivers

Abstract: Dynamic range of a digital receiver is determined by its analog and mixed signal portion (AMP). Among parameters that characterize the receiver dynamic range, single-tone dynamic range and two-tone dynamic range are usually most important. The ultimate value of the dynamic range upper bound is limited by acceptable power consumption of the receiver AMP. Since expanding the dynamic range usually significantly increases the receiver power consumption, ability to calculate the minimum required dynamic range is very important. An approach to a closed-form solution of the problem is discussed in this paper. Another problem discussed in the paper is achieving the maximum potential dynamic range of a digital receiver. This requires combined use of both well-known and novel methods of dynamic range improvement. The methods include proper selection of the receiver sampling frequency, filtering and utilization of the signal energy during sampling, reduction of the quantization step and increase in the effective number of bits in the receiver A/D, rejection of the strongest interfering signal as close as possible to the antenna, etc.

System and method for a MEMS sensor

Abstract: According to an embodiment, a sensor circuit includes a sigma-delta analog to digital converter (ADC), a dithered clock coupled to the sigma-delta ADC, and a supply voltage circuit coupled to the sigma-delta ADC The sigma-delta ADC is configured to be coupled to a low frequency transducer, and the dithered clock is configured to control of the sigma-delta ADC based on a dithered clock signal