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Showing papers on "Electron-beam lithography published in 1978"


Journal ArticleDOI
TL;DR: In this article, the authors used high-resolution scanning transmission electron microscopy (STEM) to expose the resist and the samples were mounted on 60 nm-thick Si3N4 membrane substrates.
Abstract: 25‐nm‐wide lines and spaces have been fabricated in 22.5‐nm‐thick films of PdAu (40 : 60) using electron‐beam exposure and polymethylmethacrylate (PMMA) resist. A high‐resolution scanning transmission electron microscopy (STEM) was used to expose the resist and the samples were mounted on 60‐nm‐thick Si3N4 membrane substrates. Previously, the smallest metal structures formed with a resist process were 60 nm wide with spaces between the lines several times larger than the lines. The results presented here show that 25‐nm lines can be fabricated with a center to center spacing of 50 nm.

130 citations


Patent
28 Jul 1978
TL;DR: In this paper, a method of grain-orienting the crystal structure of a layer of semiconductor material by application of a raster scanning electron beam to a layer which has been previously formed on a substrate, such as by sputter-plasma film deposition, is described.
Abstract: A method of grain-orienting the crystal structure of a layer of semiconductor material by application of a raster scanning electron beam to a layer of polycrystalline semiconductor material which has been previously formed on a substrate, such as by sputter-plasma film deposition. The method comprises electron beam lithography computer-applied to the crystal growth and orientation of a polycrystalline thin sheet of silicon or other semiconductor material.

35 citations


Patent
15 Aug 1978
TL;DR: In this article, a method and means for x-ray lithography which utilizes means for producingn a vacuum system a high-temperature plasma from which soft x-rays are emitted.
Abstract: A method and means for x-ray lithography which utilizes means for producingn a vacuum system a high-temperature plasma from which soft x-rays are emitted. The x-rays pass through a mask exposing an x-ray resist on a substrate to produce the desired pattern on the substrate. The x-ray spectrum has a significant energy in the 1-5 keV range. These x-rays pass through the support layer of the mask, stop in the pattern material (gold) of the mask or, where the pattern material is lacking, are absorbed adequately by the x-ray resist. Since there is very little energy above 5 keV, there is little if any substrate damage due to the x-rays.

34 citations


Patent
13 Nov 1978
TL;DR: In this article, the authors used electron beam lithography and dry processing techniques to produce semiconductor devices with gate dimensions as small as 0.25 microns square using N-channel, metal-oxide-semiconductor (NMOS) field effect transistors (FETs).
Abstract: Semiconductor devices with gate dimensions as small as 0.25 microns square have been fabricated using electron beam lithography and dry processing techniques. In particular, silicon gate, N-channel, metal-oxide-semiconductor (NMOS) field-effect-transistors (FET) have been produced. The devices and the process are especially adapted to bulk silicon based transistors.

27 citations


Patent
04 Dec 1978
TL;DR: In this paper, the authors describe a process for ion beam etching fine patterns in a substrate using a protected resist mask which prevents erosion of the mask and provides improved pattern definition for the etched region.
Abstract: The specification describes a process for ion beam etching fine patterns in a substrate using a protected resist mask which prevents erosion of the mask. First, a resist pattern is formed on the surface of a substrate to expose pre-selected areas of the substrate. Next, a selected material is deposited on the resist mask at a predetermined controlled angle of incidence with respect to the surface of the mask to form a relatively thin protective layer on the resist mask, having edges and patterns replicated from the edges and patterns of the resist mask and a negligible amount of the selected material deposited on the exposed substrate. Then, a beam of ions at a chosen energy is directed through openings in the protected mask to the substrate to etch the pre-selected areas. During etching, the protective layer on the resist prevents erosion of the resist mask and provides improved pattern definition for the etched region. In a preferred embodiment, metal contacts to the etched regions are subsequently formed by depositing a selected metal from a directional source and then lifting off the resist and the undesired metal.

26 citations


Journal ArticleDOI
TL;DR: In this article, laser-heated plasmas were used to replicate features as fine as 750 nm in the positive resist polybutene-1-sulfone (p.b.s.).
Abstract: X-rays from laser-heated plasmas were used to replicate features as fine as 750 nm in the positive resist polybutene-1-sulfone (p.b.s.). The measured sensitivities of p.b.s. to pulsed and d.c. X-rays (≈ 109 ratio in exposure rate) are similar (no reciprocity loss). Laser-plasma X-rays produced only small (0.25 V) flat-band shifts in m.o.s. capacitors at irradiation levels sufficient to expose p.b.s.

26 citations


Journal ArticleDOI
TL;DR: In this paper, integrated injection logic gates have been fabricated using electron-beam lithography and ion implantation and a factor of five reduction in gate area over conventional designs was achieved by using minimum linewidths of 1.25 µm.
Abstract: Integrated injection logic gates have been fabricated using electron-beam lithography and ion implantation. A factor of five reduction in gate area over conventional designs was achieved by using minimum linewidths of 1.25 µm. Average propagation delay of 6 ns at 100 µA/gate injector current and speed-power product of 0.13 pJ at 5 µA have been measured on five collector, stick geometry, n+guard ring device structures. The delay time is a factor of three and the speed-power product is a factor of five better than typical conventionally sized structures fabricated with photolithography. A minimum delay of 3.6 ns has been achieved on five collector device structures designed for maximum speed.

23 citations


Journal ArticleDOI
TL;DR: In this paper, a computer program was developed for the three-dimensional calculation of the absorbed energy density in polymer films on substrates in electron beam lithography, based on the reciprocity principle proposed by Chang.
Abstract: A computer program has been developed for the three-dimensional calculation of the absorbed energy density in polymer films on substrates in electron beam lithography. In this calculation the Monte Carlo results have been used for the radial energy intensity distribution for a point source electron beam. The program is based on the reciprocity principle proposed by Chang. Some exposure experiments have been conducted with an electron resist of PMMA (polymethyl methacrylate) for isolated patterns in the from of a line of finite length (8.1 µm) as well as of a rectangle (3.1×8.1 µm2) in order to check the reliability of the calculations. Operating beam voltages used for the investigation are 14 and 20 keV. The electron resist thickness is 8000 A. Relatively good agreement has been obtained between the calculated and the experimental results. This program is applicable to an arbitraty pattern, and therefore it will be useful for investigations of the proximity effect in electron beam lithography.

18 citations


Journal ArticleDOI
TL;DR: In this paper, a 4-kbit CCD memory array has been fabricated using electron-beam lithography for the high-resolution patterns and projection lithography to define the low-resolution features.
Abstract: A 4-kbit CCD memory array has been fabricated using electron-beam lithography for the high-resolution patterns and projection lithography to define the low-resolution features. The basic CCD cell size is 3.2 µm × 4.2 µm consisting of a storage area 2.4 µm × 3.6 µm with a 0.8-µm barrier and a 0.6-µm channel stop. To make these small CCD's, as well as the associated short-channel MOSFET's, we modified the conventional MOS wafer processing. The new process for two-level polysilicon gates requires six electron-beam levels with a minimum resist feature of 0.3 µm. Alignment of the electron-beam patterns uses Ta benchmarks which we found to be compatible with MOS devices. Testing of the 4-kbit array and other shift resisters showed submicrometer channel-stops and barriers are feasible while maintaining low channel-to-channel crosstalk and charge-transfer efficiency greater than 0.9995. In addition, low capacitance output circuits defined by electron-beam lithography can detect the small number of charges in the high-resolution CCD's and amplify the signal sufficiently to recirculate the data.

12 citations


Proceedings ArticleDOI
01 Jan 1978
TL;DR: In this paper, the fabrication of 1 micron minimum linewidth FET polysilicon devices and circuits was described for the tight dimensional groundrules achievable using direct wafer write scanning electron beam lithography.
Abstract: We describe the fabrication of 1 micron minimum linewidth FET polysilicon devices and circuits. These were designed for the tight dimensional groundrules achievable using direct wafer write scanning electron beam lithography. This paper emphasizes the vector-scan electron beam technology and processing, while other papers in this conference(1) discuss other aspects of the work. Different types of 1 micron FET chips were written on 57mm Si wafers using a totally automated electron beam system(2) which performs table stepping, registration to fiducial marks, and pattern writing in a vector scan mode (individual shape basis) with control of exposure dose for individual shapes. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance jumps between shapes. A novel two-layer positive resist system has been developed to achieve reproducible lift-off profiles over topography and better linewidth control (typically <0.1 micron). A level to level registration accuracy groundrule of 0.3 micron has been satisfied with achievement of typical alignment of 0.1-0.2 microns between any two levels.

9 citations


Patent
27 Mar 1978
TL;DR: In this article, the authors measure the electric current variation caused by a shift in the relative position between the electron beam and a shield by measuring the time which corresponds to the electric-current variation.
Abstract: PURPOSE: To seize the size of an electron beam by measuring the time which corresponds to the electric-current variation caused by a shift in the relative position between the electron beam and a shield. CONSTITUTION: Electron-beam checker 16 is placed where an electron beam strikes, and in this state, the one-dimensional deflection of the electron beam is done. The electron beam is deflected to pass through the slit of shield 18, so that when the diameter of the slit opening is supposed to be greater than that of the electron beam, the waveform of the electronic current passing though the opening will be shown in the figure. Time t 2 -t 1 or t 4 -t 3 is in proportion to the size of the electron beam. COPYRIGHT: (C)1979,JPO&Japio


Journal ArticleDOI
TL;DR: In this paper, an integrated injection logic (I2L) gate has been fabricated using electron-beam lithography, ion implanatation, and advanced I2L design technology.
Abstract: Integrated injection logic (I2L) gates have been fabricated using electron‐beam lithography, ion implanatation, and advanced I2L design technology. Minimum line widths of 1.25 μm were used to delineate structures five times smaller in area than obtained with conventional design rules. Improved geometry control was achieved by using shallow diffusions and thin epi (∠1.2 μm). PBS positive resist was used to pattern and etch oxides and TI309 negative resist was used to mask etching of Al/Si and Al/Cu metallizations. Thick PMMA was used as an implant mask for 300‐keV p− intrinsic base implant. Chip‐by‐chip alignment of 2.5×2.5 mm2 fields yielded level to level registration accuracy of 0.2–0.4 μm. Using a 25‐stage ring oscillator as a test vehicle, gate delays of ∠6 ns at 100 μA/gate have been measured on 5‐collector, n+ guard ring device structures. These devices also yielded a speed–power product five times lower than that of similar conventionally sized devices.

Journal ArticleDOI
TL;DR: One hundred and twentyeight-bit, two-phase, high-density CCD linear shift registers with double-level polysilicon overlapping gate electrodes have been fabricated using electron-beam lithography for all levels of pattern delineation as discussed by the authors.
Abstract: One hundred and twenty‐eight‐bit, two‐phase, high‐density CCD linear shift registers with double‐level polysilicon overlapping gate electrodes have been fabricated using electron‐beam lithography for all levels of pattern delineation. The polysilicon gate electrodes are 0.15 mil long and the channel widths on two shift registers are 0.25 and 0.06 mil. The critical registration accuracy is ±1500 A. These represent cell sizes of 0.1 mil2 corresponding to packing densities of 10–20 million bits/in. Charge transfer efficiency with VΦ=10 V and without fat zero is at least 0.9997 for 0.05 mil2 shift register. The low, uniform leakage current (1.5–4 nA/cm2) observed in CCD’s fabricated by electron‐beam lithography compares favorably with those fabricated using optical lithography and larger geometry sizes. This indicates that no significant electron beam induced residual damage is present in these CCD structures.

Proceedings ArticleDOI
W.R. Hunter1, L. M. Ephrath, W.D. Grobman, C.M. Osburn, B.L. Crowder, A. Cramer, H.E. Luhn 
01 Jan 1978
TL;DR: In this article, an n-channel silicon gate technology using electron-beam lithography with minimum dimensions of 1 µm was implemented for FET logic applications, which employs semi-recessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques and reactive ion etching (RIE).
Abstract: An n-channel silicon gate technology, using electron-beam lithography with minimum dimensions of 1 µm, has been implemented for FET logic applications. The six mask process employs semi-recessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques and reactive ion etching (RIE). A description of the process is given, with particular emphasis or topographical considerations. Implementation of a field etchback after source and drain implant to eliminate a low thick-oxide parasitic device threshold is also discussed.

Proceedings ArticleDOI
06 Sep 1978
TL;DR: In this paper, a two-stage fabrication process was developed which has produced previously unobtainable high frequency surface acoustic wave (SAW) devices, and the design-to-test cycle time has been shortened significantly to allow an effective interactive design procedure.
Abstract: A two step fabrication process was developed which has produced previously unobtainable high frequency surface acoustic wave (SAW) devices. In addition, the design-to-test cycle time has been shortened significantly to allow an effective interactive design procedure. The SAW structure places some of the most stringent precision requirements on current electron-beam lithography since finger placement errors are directly related to phase errors in the electrical performance of bandpass or pulse compression filters. A form of double precision is implemented in the interface software to enable successful patterning of the monotonic variation in line width from less than 0.4 µm to more than 0.9 µm required for a 1 to 2 GHz pulse compressor. Compensation for proximity effects due to the electron beam profile was also implemented. Alignment accuracy within a field is controlled to within ±250 A and field placement is accomplished via a laser interferometer controlled stage. Several alternative processes, including direct slice writing, reverse lift off, and X-ray lithography are compared. Once the E-beam master is generated, large area contact replication is achieved using a modified conformable mask printer. This process has extended the range of SAW device performance beyond 2 GHz in a fundamental mode which represents a significant advancement in microfabrication. Three day turnaround from design to packaged devices was demonstrated using this technique.


Proceedings ArticleDOI
01 Jan 1978
TL;DR: In this paper, the problem of photo electron spreading in PBS is discussed, and the slope of the resist side wall is shown to be a more serious problem in limiting resolution than the conventional side wall slope.
Abstract: CMOS processing with x-ray lithography is reviewed. X-ray source selection, resist handling techniques and dry etching methods are discussed. The problem of photo electron spreading in PBS is also discussed. Slope of the resist side wall is shown to be a more serious problem in limiting resolution.

Proceedings ArticleDOI
06 Sep 1978
TL;DR: In this paper, the authors explored methods of compensating for the proximity effect in submicrometer patterns exposed on a vector-scan exposure system and discussed two approaches which can be utilized to process figure specifications prior to exposure time to compensate for proximity effect.
Abstract: The proximity effect in electron-beam lithography describes enhanced resist exposure due to electron scattering in the resist and backscattering from the substrate. Since good edge definition requires high resist contrast, the proximity effect can substantially alter developed pattern shapes and fidelities. This effect increases as pattern sizes decrease and becomes rather severe for submicrometer geometries. We have explored methods of compensating for the proximity effect in submicrometer patterns exposed on a vector-scan exposure system. This paper discusses two approaches which can be utilized to process figure specifications prior to exposure time to compensate for the proximity effect. We also show how these approaches fit into an overall program of pattern specification and exposure.© (1978) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Journal ArticleDOI
TL;DR: In this article, a layout generation system that may be used to produce masters using either photolithography or electron beam lithography is described, which is centred around a high level pattern specification language that allows considerable latitude in pattern definition.


Journal ArticleDOI
01 Dec 1978
TL;DR: In this article, a precision electron beam exposure system, EB52, has been developed for mask making and direct wafer exposure for less than 2 03BCm minimum pattern size, which is achieved with deflection distortion correction and beam shift correction using a standard mark on the X-Y stage.
Abstract: 2014 A precision electron beam exposure system, EB52, has been developed for mask making and direct wafer exposure for less than 2 03BCm minimum pattern size. This paper describes the system control method and performance of the system components which are designed considering positioning error factors, and an example of chrome mask fabrication by the system, in which overlay accuracy of ± 0.2 03BCm has been achieved with deflection distortion correction and beam shift correction using a standard mark on the X-Y stage. REVUE DE PHYSIQUE APPLIQUÉE TOME 13, DÉCEMBRE 1978,