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Showing papers on "Electronic circuit simulation published in 1979"



Patent
18 Dec 1979
TL;DR: In this paper, the authors proposed a delay control circuit in the simulator of a digital satellite circuit to generate a round trip delay by providing a variable delay circuit in a TDMA terminal station unit.
Abstract: PURPOSE:To perform a simulation close to actuality by generating a round trip delay by providing a variable delay circuit in the simulator of a digital satellite circuit. CONSTITUTION:This system is constituted by transmission TDMA terminal station unit 1 which consists of base band modulator 11 and TDMA modulator 12, receiving TDMA terminal station unit 5 which consists of TDMA demodulator 31 and base band demodulator 32, error rate measuring unit 6, and digital satellite simulator 9 which consists of simulating satellite relay 21, random noise generator 22, adder circuit 23 where noise generated from generator 22 is added, variable delay circuit 24 which consists of a large scale random access memory, etc., and delay control circuit 25 which controls and delay time of circuit 24.

2 citations


ReportDOI
01 Nov 1979
TL;DR: The feasibility is determined of using small computer systems (including programmable desktop calculators and minicomputers) for interactive electronic circuit simulation and analysis techniques are presented which conserve memory and advantage of the idiosyncrasies of these small computers.
Abstract: : The feasibility is determined of using small computer systems (including programmable desktop calculators and minicomputers) for interactive electronic circuit simulation. Several aspects of the simulator architecture are considered: the computer language, the data word format, the computing speed, and the computer memory configuration. Interactive circuit simulation on programmable desktop calculators is investigated using simulator program BIAS-D (BASIC), written in BASIC for HP9830A desktop calculator. Analysis techniques are presented which conserve memory and advantage of the idiosyncrasies of these small computers. Interactive-mode circuit simulation and batch-mode simulation on minicomputers are compared relative to the simulator architecture and required simulation speed. The more significant speed- and memory-dependent algorithms, used in circuit simulators are compared in detail. Also compared are the execution speeds of several different minicomputer systems, including the HP2100, the PDP 11/45, and the PRIME 400. The speed and memory requirements of these minicomputers executing BIAS-D are compared to an IBM 370/168 also executing BIAS-D. A new method for computing small-signal frequency response is introduced. Because complex arithmetic is not required, this technique is particularly suited to minicomputer simulators and requires minimal additional memory when implemented in a circuit simulator with a transient analysis capability. The frequency response of both linear and nonlinear circuits can be modeled, as can that of high-Q circuits. Magnitude and phase errors of less than 1 percent and 0.5 degrees, respectively, are easily attainable.

1 citations



Journal ArticleDOI
D. Gambart1, G. Maral1
TL;DR: An improved algorithm is presented using BDF formulas given by Brayton et al. and has been implemented in the IMAG electronic circuit simulation program, reducing computer time by controlling the number of Newton iterations, theNumber of integration steps, and thenumber of Jacobian matrix evaluations.
Abstract: The resolution of systems of stiff differential equations is required in the transient analysis of a large electronic network simulation. Resultant stability problems and the methods used in solving first order stiff nonlinear differential equations are reviewed. An improved algorithm is presented using BDF formulas given by Brayton et al. IEEE Vol 60 (1972) pp 98–108 and has been implemented in the IMAG electronic circuit simulation program. Reducing computer time has been achieved by controlling the number of Newton iterations, the number of integration steps, and the number of Jacobian matrix evaluations without producing additional errors or instability phenomena. Experimental results are shown.