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Showing papers on "Electronic circuit simulation published in 1983"


Journal ArticleDOI
TL;DR: Techniques for analyzing the signal transmission properties of long resistive interconnects on integrated circuits are presented and guidance is provided for selecting the number of elements needed to accurately simulate performance under various conditions.
Abstract: Techniques for analyzing the signal transmission properties of long resistive interconnects on integrated circuits are presented. Because accurate measurements of propagation characteristics on chip are difficult to make, RC transmission line theory is used to establish exact performance. The results of various simulations are compared to this theoretical performance. Guidance is provided for selecting the number of elements needed to accurately simulate performance under various conditions.

76 citations


Journal ArticleDOI
T. Shima1, H. Tamada, Ryo Luong, Mo Dang
TL;DR: This paper describes a method for connecting an M OSFET 2-D device simulator to a circuit simulator via a 3-D table look-up MOSFET model via a proposed monotonic piecewise cubic interpolation technique.
Abstract: This paper describes a method for connecting an MOSFET 2-D device simulator to a circuit simulator via a 3-D table look-up MOSFET model. The computational cost of the device simulator is drastically reduced by a proposed monotonic piecewise cubic interpolation technique. With this technique, the device simulator needs to calculate only 100 ~ 200 points to make up an accurate 3-D table look-up MOSFET model. The computational time necessary for the interpolation is only about one third of the time for calculating one current point by the device simulator.

64 citations


Journal ArticleDOI
T. Tokuda1, K. Okazaki, K. Sakashita, I. Ohkura, T. Enomoto 
TL;DR: The new timing verification method using the delay model is evaluated with respect to delay-time accuracy and execusion time in a logic LSI and circuit simulator accuracy is obtained in the short computer run time of a logic simulator.
Abstract: The propagation delay time of the ED MOS logic gate is precisely analyzed considering input waveform and loading conditions. According to theoretical consideration and circuit analysis, the rise mode delay time tpLH is approximated as a function of the output capacitance of only the gate concerned. The fall mode delay time t.pHL is determined by the input capacitance and output capacitance of the gate concerned. These results allow the easy implementation of the delay model into a logic simulator. A precise delay simulation is attained by considering the delay components, corresponding to each input node, at the output side of the logic element. The propagation delay times of the transmission gate are precisely analyzed. The operations of the transmission gate are divided into two modes; synchronous mode and asynchronous mode. Corresponding to each mode, the transmission gate, the preceding gate, and the succeeding gate have two kinds of delay times. To simulate delay times of each gate precisely, models which treat these three logic elements as one primitive element in a logic simulator have been proposed. The new timing verification method using the delay model is evaluated with respect to delay-time accuracy and execusion time in a logic LSI. Through this method, circuit simulator accuracy is obtained in the short computer run time of a logic simulator.

30 citations


Book ChapterDOI
12 Sep 1983
TL;DR: The modern electronic is in the future mainly an integrated electronic in form of LSI or VLSI chips that includes analogue circuit functions, digital circuit functions and the combination of both.
Abstract: The modern electronic is in the future mainly an integrated electronic in form of LSI or VLSI chips. It includes analogue circuit functions, digital circuit functions and the combination of both.

2 citations



Journal ArticleDOI
TL;DR: Preliminary comparisons between RELAX and the standard circuit simulator SPICE2 have shown that RELAX is a fast and reliable circuit simulator.
Abstract: Algorithms and techniques used in RELAX are described. RELAX is a time domain MOS digital circuit simulator based on a new analysis method called Waveform Relaxation Method 1 which exploits decomposition techniques. Preliminary comparisons between RELAX and the standard circuit simulator SPICE2 have shown that RELAX is a fast and reliable circuit simulator.