Showing papers on "Electronic circuit simulation published in 1984"

A general approach to sampled-data modeling for power electronic circuits

Abstract: A general, sampled-data representation of the dynamics of arbitrary power electronic circuits is proposed, to unify existing approaches· It leads, via compact and powerful notation, to disciplined modeling and straightforward derivation of small-signal models for perturbations about a nominal cyclic steady state. Its usefulness is further illustrated by considering the representation and analysis of a class of symmetries in circuit operation. Results of application of this methodology to modeling the small-signal dynamics of a series resonant converter are described. The results correlate well with simulation results obtained on MIT's Parity Simulator. What is of more significance to the theme of this paper is the fact that the small-signal model is obtained in a completely routine way, starting from a general formulation and working down to the actual circuit; this contrasts with the circuit-specific analyses that are more typical of the power electronics literature. The paper also discusses the automatability of the above procedure, pointing out that the key ingredients for automatic generation of dynamic models from a circuit specification are now available.

An algorithm for CMOS timing and area optimization

Abstract: Delay-time optimization for integrated circuits is discussed. A design truly optimized for delay time is seldom practical because the silicon area increases very rapidly when the minimum delay time is approached. The author presents an algorithm which facilitates an intelligent compromise between the delay time and the silicon area of a logic chain. A computer software based on this algorithm can interactively assist the designer in the selection of logic pattern, the number of stages, and the sizes of the transistors. Some basic assumptions are made in this algorithm in order to keep the mathematics manageable. Consequently, some random parameters related to layout and interconnection are not addressed. The intended use of this algorithm is to guide the designer to arrive at an approximately optimized design during the logic definition stage and before the layout stage. Later, when the layout is completed, a circuit simulator should be used to fine-tune the design by incorporating these random layout parameters.

A sensitivity analysis of SPICE parameters using an eleven-stage ring oscillator

Abstract: SPICE is a circuit simulator which predicts node voltages and currents as a function of time from device model parameters. Model parameters are determined by the manufacturing process, but process-induced variations in these parameters occur within a chip or from chip to chip. Values for the model parameters used in simulators are usually obtained from measurements on test structures along the periphery of the circuit or in test chips located at several sites on the product wafer. This paper presents examples of how well model parameters extracted from a test chip can predict the AC response of a dynamic circuit element (MOS ring oscillator) on the same wafer. Simulation results show which model parameters are critical to performance. A comparison between measurement and simulation results is given and the importance of intrachip and intrawafer parameter variations is discussed. For the samples tested, the polysilicon gate linewidth variation was determined to be the primary cause of the ring oscillator frequency variation.

Circuit Simulation Code Generation by Computer Algebra.

Abstract: CSCG (Circuit Simulation Code Generator) is a circuit simulator based on computer algebra system (REDUCE 3.0). Circuit specifications are given by commands which generate the Hamiltonian H and the dissipating function D of the circuit. Partial derivatives of H and D are computed symbolically by REDUCE so as to generate the equations of motion. CSCG is written in REDUCE and automatically generates FORTRAN code for numerical integration, either using Runge-Kutta or Gear's method. The partial derivatives needed in the latter method are also computed symbolically. In comparison with conventional table-driven simulators, the code generated by CSCG performs simulation much faster (similar to compiled versus interpreted code), and it is believed to be much easier to implement and to use. CSCG is now extensively used for simulations of Josephson junction circuitries.

CAD in electronics

Abstract: CAD of electronic assemblies is discussed. The various language levels used to specify system architecture and to permit behavioural simulation is described, as is the development of circuit design. Future developments are suggested.

A sensitivity analysis of SPICE parameters using an eleven-stage ring oscillator

Abstract: SPICE is a circuit simulator which predicts node voltages and currents as a function of time from device model parameters. Model parameters are determined by the manufacturing process. Process-induced variations in these parameters occur within a chip or from chip to chip and cause corresponding variations in circuit performance. Values for the model parameters used in simulators are usually obtained from measurements on test structures which are found along the periphery of the circuit or in test chips located at several sites on the product wafer. Because of the spatial separation between test structures and the circuits of interest, differences between measured and simulated performance can occur. This paper presents examples of how well model parameters extracted from a test chip can predict the ac response of a dynamic circuit element (ring oscillator) on the same wafer. Simulation results show which model parameters are critical to performance. A comparison between measurement and simulation results is given and the importance of intra-chip and intra-wafer parameter variations is discussed. For the samples tested, the polysilicon gate linewidth variation was determined to be the primary cause of the ring oscillator frequency variation.