Showing papers on "Electronic circuit simulation published in 1986"

A CAD-oriented non-quasi-static approach for the transient analysis of MOS ICs

Abstract: The proposed approach, which considers the MOS transistor as a four-terminal device and takes into account short-channel effects, has been implemented in the circuit simulator SPICE. It is shown that the results predicted from this CAD-oriented approach are in good agreement with those achievable with a numerical procedure. It is also found that, using the new model in SPICE, the evaluation of transients in some high-precision circuits gives results significantly different from those expected from standard quasi-static formulations.

Hot-carrier generation in submicrometer VLSI environment

Abstract: Submicrometer MOSFETs may suffer from reliability degradation, which has a strong correlation with substrate current. In order to know what is happening to substrate current in a VLSI environment, a substrate-current circuit simulator is developed. The simulator is applied to MOS unit circuit blocks, VLSI static memories, and dynamic memories, and their hot-carrier duty ratios are calculated. A new circuit technology, called normally-on enhancement MOSFET insertion (NOEMI), is proposed which can suppress hot-carrier generation. Several design implications for submicrometer VLSIs are obtained through the analysis.

Process and device modeling

Abstract: Preface. 1. Physical Models and Numerical Methods for VLSI Process Simulation (B. R. Penumalli). 2. Ion Implantation Models for Process Simulation (H. Ryssel, J. P. Biersack). 3. Simulation of Lithography (A. R. Neureuther, W. G. Oldham). 4. Physical Models for Numerical Device Simulation (G. Baccarani et al.). 5. Basic Theory of Stationary Numerical Models (M. S. Mock). 6. New Approaches to Submicron Device Modelling (A. Yoshii, M. Tomizawa). 7. Computational Aspects of Semiconductor Device Simulation (R. E. Bank et al.). 8. On Modeling MOS-Devices (S. Selberherr). 9. Three-Dimensional Device Simulation using a Mixed-Process/Device Simulator (N. Shigyo, R. Dang). 10. Numerical Model Hierarchies (H. K. Dirks). 11. The Application of Process and Device Simulation Tools to VLSI Development (E. J. Prendergast, P. Lloyd, W. T. Cochran). 12. Compact MOSFET Modeling (F. M. Klaassen). 13. Compact Bipolar Transistor Modeling (H. C. De Graaff). 14. Device and Circuit Simulator Integration Techniques (T. Shima).

Modeling MOS VLSI circuits for transient analysis

Abstract: Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.

A Workstation-Based Mixed Mode Circuit Simulator

Abstract: A new mixed mode simulator is described, which combines a behavioral timing simulator, a switch level simulator, and a new circuit-level simulator based upon the ADEPT timing simulation algorithm. These simulation algorithms are combined into a single, consistent, interactive MOS simulator. In addition, STAFAN fault simulation is provided at the transistor level to grade vectors to be used in the testing phase of design. In this paper, each algorithm is described as well as the interfacing required between each of the simulation methods. Several examples are presented to demonstrate the utility of the L-Simulator. Circuit simulation is performed on a wide range of CMOS counter sizes, from 2 to 32 bits, showing tremendous reductions in CPU time as compared to SPICE, without loss in accuracy. A novel multi-mode simulation facility is also introduced, further decreasing the CPU time requirements for simulation. A second example shows how the performance and area of a CMOS latch is optimized using circuit modification techniques during simulation. Finally, a 73,200 transistor design of an 8051-like CPU is simulated in behavioral, switch level, and finally in circuit/mixed modes.

An accurate dc model of 2-DEG FET for implementation on a circuit simulator

Abstract: An accurate dc model for FET's using two-dimensional (2- D) carrier gas flow adjacent to the heterointerface is described. The model, based on novel empirical velocity-field curve, also takes into consideration a parallel conduction in a selectively doped layer. In addition, it depends primarily on physical rather than empirical parameters. The calculated results are in excellent agreement with experimental data, even for short-channel 2-D electron gas (2-DEG) FET's at 77 K. The present model will therefore be a promising candidate for implementation on a circuit simulator.

SPICE Simulation of SOI MOSFET Integrated Circuits

Abstract: A five-terminal, charge-based model for the thin-film silicon-on-insulator (SOI) MOSFET is implemented in SPICE2, thereby enabling, for the first time, proper simulation and CAD of SOI MOS integrated circuits in which the unique floating-body and back-gate-bias effects can be significant. The implementation is achieved, without having to rewrite the circuit simulator, by developing a general method for incorporating new charge-based device models into SPICE2 that utilizes user-defined controlled sources (UDCS's). The utility and computing efficiency of the SOI MOSFET model implementation are demonstrated by simulating several representative SOI MOS circuits.

A Table Model for Circuit Simulation

Abstract: Table models for SPICE-type circuit simulators have been investigated. A table model based on B-spline approximation has been implemented in our SPICE-based circuit simulator. It shows good convergence properties and allows significant reduction of model evaluation time on our vector computer. It will be used as a flexible interface between device simulation/measurements and circuit simulation in a low level CAD-system.

A SPICE Interactive Graphics Preprocessor

Abstract: This paper discusses the development and use of an interactive computer graphics interface to the SPICE circuit simulation program. This package provides for the convenient input of the circuit topology and the values of the circuit elements from the designer, and creates a structured database to store the circuit information.

An Empirical Analysis of the Performance of a Multiprocessor-Based Circuit Simulator

Abstract: Our original MSPLICE multiprocessor-based circuit simulator showed excellent efficiency with up to 10 processors. As shown in this paper, however, the efficiency of the program drops significantly when over 40 processors are used. A new generation of the MSPLICE program is described which shows high efficiency with up to 99 processors for three different benchmark circuits. Data is compared against predictions made from simulations of an ideal Gauss-Seidel machine model with unit delay, and the data as well as the model are evaluated in light of this comparison. The results from the new implementation are used to study actual limitations that arise as more processors are employed to solve the circuit simulation problem. A major problem identified is that of scheduling overhead and queue contention. Elimination of this bottleneck has led to significant performance improvement. Another bottleneck discovered in the original implementation was that of global data structure contention. Solutions for these and other problems have been implemented in MSPLICE and are currently being used to direct the continued development of the program.

A model-base comparison: GaAs/GaAlAs HBT versus silicon bipolar

Abstract: A pure model-base comparison is made between the GaAs/ GaAlAs HBT and the silicon bipolar transistor for the high-speed switching performance under ring oscillator operation. Full utilization is made of our own modeling tools, which include a "physical" one-dimensional transistor model, a hybrid model to represent a realistic device structure, and a circuit simulator to allow direct access to the physical model. Delay time versus power characteristics, as well as dynamic carrier profiles are demonstrated, with discussion about limiting factors for the switching speed.

A workstation-mixed model circuit simulator

Abstract: A new mixed mode simulator is described, which combines a behavioral timing simulator, a switch level simulator, and a new circuit-level simulator based upon the ADEPT timing simulation algorithm. These simulation algorithms are combined into a single, consistent, interactive MOS simulator. In addition, STAFAN fault simulation is provided at the transistor level to grade vectors to be used in the testing phase of design. In this paper, each algorithm is described as well as the interfacing required between each of the simulation methods.Several examples are presented to demonstrate the utility of the L-Simulator. Circuit simulation is performed on a wide range of CMOS counter sizes, from 2 to 32 bits, showing tremendous reductions in CPU time as compared to SPICE, without loss in accuracy. A novel multi-mode simulation facility is also introduced, further decreasing the CPU time requirements for simulation. A second example shows how the performance and area of a CMOS latch is optimized using circuit modification techniques during simulation. Finally, a 73,200 transistor design of an 8051-like CPU is simulated in behavioral, switch level, and finally in circuit/mixed modes.

Circuit simulation code generation by computer algebra

Abstract: CSCG (Circuit Simulation Code Generator) is a circuit simulator based on computer algebra system (REDUCE 30) Circuit specifications are given by commands which generate the Hamiltonian H and the dissipating function D of the circuit Partial derivatives of H and D are computed symbolically by REDUCE so as to generate the equations of motion CSCG is written in REDUCE and automatically generates FORTRAN code for numerical integration, either using Runge-Kutta or Gear's method The partial derivatives needed in the latter method are also computed symbolically In comparison with conventional table-driven simulators, the code generated by CSCG performs simulation much faster (similar to compiled versus interpreted code), and it is believed to be much easier to implement and to use CSCG is now extensively used for simulations of Josephson junction circuitries

Electronic circuit simulation system

Abstract: not available for EP0198729Abstract of corresponding document: US4791593A simulation system of an electronic circuit. The system comprises a memory, a processor, an interface circuit and data, address and control buses connecting these components. The memory has a first zone containing data for representing the simulated electronic circuit, a second zone containing instructions and a third calculating zone. The state of the electronic circuit is determined by the electrical potential in each node. The processor performs the instructions contained in the second memory zone. The processor is able to calculated the potential of all the nodes at a fixed time Tn, 1