Showing papers on "Electronic circuit simulation published in 1992"

State-of-the-art harmonic-balance simulation of forced nonlinear microwave circuits by the piecewise technique

Abstract: The theoretical foundations and the numerical performance of an advanced nonlinear circuit simulator based on the piecewise harmonic-balance (HB) technique are discussed. The exact computation of the Jacobian matrix for Newton-iteration based HB simulation and the related conversion-matrix technique for fast mixer analysis are formulated in a general form. Convergence problems at high drive levels are solved by a parametric formulation of the device models coupled with an advanced norm-reducing iteration. A physics-based approximation is shown to allow the HB equations to be effectively decoupled in many practical cases, bringing large-sized jobs, such as pulsed-RF analysis, within the reach of ordinary workstations. The exact Jacobian is used in conjunction with an exact formula for the gradient of the objective function, to implement an efficient broadband nonlinear circuit optimization capability. Examples are presented. >

AWESpice: a general tool for the accurate and efficient simulation of interconnect problems

Abstract: AWESpice is a tool for the efficient and accurate simulation of circuits dominated by interconnect. It accepts a general nonlinear circuit and uses the asymptotic waveform evaluation (AWE) algorithm to efficiently convert its linear interconnect portion into multiport admittance macromodels. The macromodels are then simulated in conjunction with the nonlinear devices using a modified version of the SPICE algorithm. This technique leads to a significant reduction in CPU time while retaining the benefits of a conventional circuit simulator. Some examples that have been run to show the accuracy and efficiency of AWESpice on a variety of interconnect problems are presented. >

Time-domain electromagnetic analysis of interconnects in a computer chip package

Abstract: The determination of an equivalent circuit to approximate the behavior of an interconnect in a computer package is addressed. Equivalent circuits allow the analysis of a complete interconnect path in a circuit simulator where a full-wave analysis tool would require more memory or computer time than in currently available. Two important components of an interconnect in a computer package are uniform transmission lines, such as a microstrip line or a stripline, and discontinuities in the interconnects, such as a via between two transmission lines. A methodology for deriving a frequency-dependent description of coupled transmission lines and an equivalent circuit of a via using time-domain full-wave solutions of Maxwell's equations is presented. >

Yield optimization using a GaAs process simulator coupled to a physical device model

Abstract: A physics-based large-signal GaAs MESFET model and circuit simulator has been developed to predict and optimize the yield of GaAs MESFET designs before fabrication. Device acceptance criteria include both small- and large-signal RF operating characteristics such as small-signal gain, maximum power added efficiency, and output power at 1-dB gain compression. Channel doping details are described on the basis of processing specifications for parameters such as material deposition, ion implantation, and implant annealing. Monte Carlo techniques are used to estimate yield when disturbances in the physical parameters are modeled as multivariate Gaussian distributions. The yield estimator is integrated with an optimizer so that a design can be centered for maximum yield in the presence of process disturbances. >

Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation

Abstract: The authors present an accurate one-dimensional device model for the simulation of nMOS transistors with hot-carrier-induced oxide damage. The model uses a realistic charge density distribution profile to account for the localization of the oxide-interface charge near the drain. Model simulation results obtained for nMOS transistors with hot-carrier-induced oxide damage demonstrate good agreement with the experimental data. The amount and the location of the hot-carrier-induced oxide damage are simulated by using only a few parameters, which simplifies the implementation of the model in a reliability simulation environment. The proposed model has been implemented in the iSMILE circuit simulator, and the capabilities of the model have been explored by various circuit simulation examples. The damaged-MOSFET model presented offers a simple and accurate approach for simulating the circuit behavior after hot-carrier damage. >

Full dynamic power diode model including temperature behavior for use in circuit simulators

Abstract: Presented is a new power diode model based on a HYBRID method. This method solves the differential equations describing the semiconductor partly analytically and partly numerically. All important effects including static and dynamic temperature behavior are considered. The model is implemented in the SABER [l] circuit simulator. The model has been verified for different ranges of operation.

The S-probe-a new, cost-effective, 4-gamma method for evaluating multi-stage amplifier stability

Abstract: The authors describe a generalized, automated, noninvasive, 4-gamma technique for stability analysis of multistage active circuits. It operates directly in the circuit simulator environment and eliminates all off-line calculations. This technique can be extended to n-port networks and works equally well with circuit models or S-parameter descriptions. Most importantly, it can detect special cases of instability involving active terminations. These are often missed using conventional stability analysis approaches. >

Coupling algorithms for mixed-level circuit and device simulation

Abstract: A general framework for mixed-level circuit and device simulation is described. This framework was used in the development of the simulation program CODECS (coupled device and circuit simulator). Various algorithms to couple the device and circuit simulators for DC and transient analyses have been implemented in CODECS. These algorithms are evaluated based on their convergence properties and run-time performance. This study provides guidelines for choosing a particular coupling algorithm. A modified two-level Newton algorithm is used for DC analysis, whereas a full block-LU decomposition algorithm is used for transient analysis. This combination of algorithms provides reasonable convergence and run-time performance. A simple latency scheme provides a 50% speedup. Coupling for small-signal AC and pole-zero analyses are described. >

System and method for generating electronic circuit simulation models having improved accuracy

Abstract: A system and method accurately translate a structural data file (30) that describes a complex logic circuit into a simulation model file (40) executable by a simulator (42). A net-list (34) is traversed, and the resulting model description is compiled into structural partitions including a WHEN-CONDITION partition (WC) that identify boundaries between synchronous and asynchronous subcircuits. The simulation model is also divided into execution time levels by a partitioned levelization method. Asynchronous feedback loops, which ordinarily lead to levelization failures, are correctly modeled by inserting time delay "levelers" (254, 262) into the feedback loop model. The resulting simulation model includes re-evaluation and evaluation stability checking steps (152, 230, 232, 276) that provide correct functional and timing evaluation of the simulation model.

Small-signal circuit modeling in the frequency-domain by computer-aided time-domain simulation

Abstract: The possibility of obtaining the frequency-domain dynamic model of a circuit from transient analysis data provided by a circuit simulator is shown. The computer-aided design (CAD) program FREDOMSIM, which governs the simulations, processes the output data, and supplies the results in a well suited manner for design optimization, is introduced. Feedback circuits are modeled with all their feedback loops open, so that the designer can optimize systems by proper a posteriori loop closures. The characterization with the loops closed is also given. >

Analytic transient solution of general MOS circuit primitives

Abstract: The exact analytic transient solution is presented for a general MOS circuit primitive. In the circuit primitive, I-V characteristics of transistors are modeled by quadratic equations and node voltages by piecewise-linear waveforms. The proposed MOS circuit primitive, of which an inverter is a special case, is shown to be more suitable for switch level and fast timing simulations than the commonly used inverter. For circuit simulation of medium-size digital circuits containing a few hundred transistors, the application of this analytic solution has resulted in two to three orders of speed improvement over the conventional circuit simulator. The speed improvement factor is expected to grow with the circuit size. It is also shown that the exact transient solution of a macromodel which models the charge sharing can be obtained in the same way. >

Flow-rate microsensor modelling and optimization using SPICE

Abstract: This paper presents a technique for modelling flow-rate microsensors using a circuit simulator. Our approach includes a user interface which greatly simplifies the generation of the circuit data file. The approach is very cost effective, as both electrical and thermal simulations can be performed using the same simulator. It also means that all simulations can be executed in the same design environment. The results of several simulations, which illustrate the usefulness of our method for both modelling and optimization of thermal micro flow sensors, are presented.

Simulations of CMOS circuit degradation due to hot-carrier effects

Abstract: By comparing long-term ring-oscillator hot-carrier degradation data and simulation results the authors show that a public-domain circuit simulator, BERT (Berkeley Reliability Tools), can predict CMOS digital circuit speed degradation from transistor DC stress data. Large initial PMOSFET drain current enhancement can result in initial frequency enhancement followed by an initial fast degradation due to the zero crossing effect. The relationship between circuit lifetime and transistor DC stress is examined. >

A non-quasi-static MOSFET model for SPICE-AC analysis

Abstract: Based on an approximate solution to the nonlinear current continuity equation in the channel, an analytic non-quasi-static model for long-channel MOSFETs has been derived and implemented in SPICE. The model includes the large-signal transient and the small-signal AC analyses, although only the AC model is reported. Excellent agreement in simulation results has been achieved between this work and CODECS (a mixed device and circuit simulator). The CPU time required for this work is about twice as long as that for currently available quasi-static MOSFET models in SPICE. >

A compiled-code hardware accelerator for circuit simulation

Abstract: Describes the application of compiled-code techniques to the design of a hardware accelerator for circuit simulation, offering a speedup by a factor of up to 4400 compared with a software circuit simulator running on a Sun-3/60 workstation. The preprocessing algorithms are designed for high speed, so overall simulation time is improved by a factor of up to 560. Compiled-code hardware accelerators offer several advantages. The hardware is simpler than fully hard-wired accelerators. The simplicity of the hardware makes it possible to track advancing implementation technology and to maintain the performance advantage as technology improves. The simulation algorithm is implemented in software, making it possible to implement and maintain multiple algorithms without hardware modifications. The hardware can be used efficiently, since compiled-code techniques can eliminate or statically perform operations that would be repeatedly performed in other hard-wired implementations. >

Dc analysis of nonlinear circuits using solution‐tracing circuits

Abstract: The dc driving-point and transfer characteristics of nonlinear circuits are the multivalued curves that arise from the nature of the circuit. These curves cannot be analyzed by general-purpose circuit simulators. One known method for analyzing these kinds of characteristic curves is the backward differentiation formula (BDF) curve-tracing algorithm proposed by Ushida and Chua. In this method, the circuit equations f(x) = 0, f(·): Rn+1 Rn, where the input voltage is assumed to be a variable, are analyzed by the predictor-corrector algorithm where the arc-length of the solution curve in n + 1-dimensional space is the parameter. However, it is not clear that this method is practical for large-scale circuits. In this paper, we extend the Ushida-Chua method from a practical method standpoint and demonstrate that the multivalued characteristic curves of large-scale circuits can easily be analyzed using general-purpose circuit simulators. In the proposed method, first, the solution curve in n + 1-dimensional space is projected into m + 1-dimensional space, where m ≤ n and the arc-length of this new curve is used as the parameter. Second, the relationship between the arc-length and the components of the curve is expressed by a function generator circuit, the solution-tracing circuit. Finally, transient analysis is performed using a general-purpose circuit simulator and the solution curve is traced. The effectiveness of this method is verified through several examples, including a bipolar analog IC with 296 nodes.

Method and means for communication between simulation engine and component models in a circuit simulator

Abstract: An apparatus and method for improved efficiency of operation of a circuit simulator. The simulation engine processor sends signals via flag registers to the component model processors to indicate which type of response is required from each component model. The component model processors send back only the requested response, thus minimizing processing time by avoiding generating response types that are not needed. Flexibility is enhanced by centralizing tasks in the simulation engine rather than in the component models, in order to facilitate experimentation and variation in circuit configurations without extensive modifications of component model design.

AWE macromodels of VLSI interconnect for circuit simulation

Abstract: Asymptotic Waveform Evaluation (AWE) has been successfully applied to the evaluation of linear(ized) models of digital system interconnect. What remains is to interface AWE models with the nonlinear rnodels of drivers and terminations that must be taken into account in order to obtain accurate timing information of the overall circuit/system. This paper describes an approach for obtaining time-domain macromodels of linear RLC interconnect that can be easily integrated into any circuit simulator. Based on generalized n-port descriptors, the technique can also be utilized to efficiently synthesize accurate driving-point models that reflect the loading characteristics of complex interconnect systems.

Systematic method for obtaining state-space representation of nonlinear dynamic circuits using MNA

Abstract: The letter presents a generalised approach for obtaining the state-space representation of nonlinear dynamic circuits using modified nodal analysis (MNA). No graph-theoretical method is required. The proposed approach allows a considerable reduction of circuit MNA equations. The method is useful when we consider development and/or improvement of a general-purpose circuit simulator such as SPICE

UNIFIED GaAs MESFET MODEL FOR CIRCUIT SIMULATIONS

Abstract: We describe a new, unified model for MEtal Semiconductor Field Effect Transistors (MESFETs) which covers all ranges of operation, including the subthreshold regime. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics are described by continuous, analytical expressions with relatively few, physically based parameters. The model includes effects such as velocity saturation, parasitic series resistances, the dependence of the threshold voltage on drain bias, finite output conductance in saturation, and temperature dependence of the device parameters. We also describe a parameter extraction routine which allows the model parameters to be derived in a straightforward fashion from experimental data. The model has been incorporated into our new circuit simulator AIM-Spice. The new device characterization is applied with good results to a typical ion-implanted GaAs MESFET and a delta-doped MESFET.

Electrical design inspection: A methodology for using circuit simulation in the design and development of electronic power supplies

Abstract: The authors present an electrical design inspection (EDI) methodology that combines advanced power circuit simulation techniques and RISC (reduced instruction set computing) workstation hardware to use simulation in the day-to-day design of electronic power supplies. This methodology makes use of circuit simulation to detect design faults in electronic power supplies and prevent them from propagating further in the product realization process. A hierarchy of inspections which form the basis of EDI methodology, is introduced. The methodology has been embedded in a prototype electrical design inspection system which has been tested on a Sun Sparcserver 4/490 dedicated to circuit simulation. The power of this methodology has been illustrated by its application to a self-oscillating variable-frequency DC-DC power converter with peak current control. It is demonstrated that EDIS can automatically execute inspections requiring an accurate determination of the steady-state solution of the circuit, and process these results. The steady-state accelerator capability within the SIMPLIS circuit simulator has made it possible to achieve this in an unprecedentedly short CPU time. >

A boundary-element approach to transient simulation of three-dimensional integrated circuit interconnect

Abstract: The authors demonstrate that boundary-element techniques can be used to perform very efficient transient simulation of three-dimensional interconnect structures, fast enough to easily be included in a circuit simulator. Two boundary element approaches are investigated, and it is shown that the most straight-forward approach leads to unacceptable discretization errors and a less intuitive second approach yields good results even with coarse surface meshes. Results of numerical experiments demonstrating the effectiveness of the second approach in calculating cross-talk are presented. >

Time domain electromagnetic analysis of a via in a multilayer computer chip package

Abstract: A methodology for deriving an equivalent circuit of a via in a multilayer computer chip package using a time-domain full-wave solution of Maxwell's equations is presented. The approach is general and its applicability is limited by the ability of the circuit simulator to model frequency-dependent elements. To accurately model the curved geometry, the nonorthogonal FDTD (finite-difference time-domain) algorithm is employed instead of the conventional FDTD method because it provides a piecewise-linear model of curved surfaces, and, with a variable mesh density, it can represent complicated structures without an excessive number of unknowns. The nonorthogonal FDTD results were validated with measurements, and an equivalent circuit model was developed from the results. >

Computationally efficient methods for accurate timing and reliability simulation of ultra-large MOS circuits

Abstract: A new approach to MOS circuit fast timing simulation is shown in this thesis. A generic MOS circuit primitive is shown along with the exact analytic solution of its state equation, a nonlinear Ricatti equation. A fast timing digital CMOS circuit simulator ILLIADS has been developed using the generic circuit primitive as well as its exact analytic solution. ILLIADS has been shown to be superior to other fast MOS timing simulators tested in both accuracy and speed. A modified waveform relaxation method for handling circuits with feedbacks is also presented in this thesis. A new algorithm taking advantages of event-driven technique and waveform relaxation method has been developed and applied. With this algorithm, simulation of a collection of ISCAS89 benchmark circuits reveals that the speedup of ILLIADS over SPICE is roughly 3N, where N is the number of transistors in a circuit. To incorporate the channel length modulation effect, an accurate and efficient method has also been developed. With this method, channel length modulation is handled with only a 10% speedup penalty. ILLIADS has been able to simulate a combinational circuit consisting of 235,000 transistors for one cycle output in 10.5 minutes real time in a workstation environment. Also presented in the thesis is a new first-time approach to fast circuit reliability simulation using a simple damaged transistor model. The new approach has made possible accurate and fast reliability simulation of large MOS circuits.

Circuit performance optimization and model fitting based on simulated annealing

Abstract: An efficient new method, based on the coupling between an enhanced simulated annealing algorithm and the SPICE-PAC ‘open’ circuit simulator, is proposed for minimizing objective functions describing circuit performance optimization problems or component model fitting to experimental data. To keep the number of objective function evaluations and CPU times to the lowest possible level, we focus our attention on two features: first, we build an original partitioning technique for splitting large n-dimensional problems; then we carefully study variables discretization, (which is necessary for applying the simulated annealing method to continuous problems). To illustrate the efficiency of our method, we show how to determine the 40 MOS transistor model parameters, through fitting the model to experimental data.

Object oriented design of a power electronics circuit simulator

Abstract: The features of object oriented programming (OOP) are explained and contrasted with the traditional procedural programming paradigm. Incorporating any or all of the OOP features of encapsulation, polymorphism and inheritance results in faster, less error prone, code implementation which promotes code reuse with the further benefit of ease of maintainability. The basic functions of a power electronics circuit simulator are described. A class structure for the simulator is outlined. This class structure has been successfully implemented using the C++ language which supports OOP. Experience with this project has indicated that C++ shines in numerical applications in comparison with FORTRAN and C. >

One-dimensional transient device simulation using a direct method circuit simulator

Abstract: A novel approach is presented for incorporating the transient solution of one-dimensional semiconductor drift-diffusion equations within a general circuit simulation tool. This approach allows simple representation of localized carrier transport models of simulated devices through equivalent circuit elements such as voltage-controlled current sources and capacitors. As the device-level simulation is carried out by the circuit simulator using an equivalent circuit representation, this approach also lends itself to mixed-mode simulation of devices and circuits. It has been shown that one-dimensional device structures can be simulated with an acceptable computational cost. The device simulation model described here has been implemented in the general-purpose direct method circuit simulation program iSMILE. The applications of the proposed device simulation approach are demonstrated by simulation examples, including the drift and diffusion of excess carriers generated by a localized light pulse in a GaAs p-i-n diode structure. >

Circuit simulation device

Abstract: PURPOSE:To perform the highly accurate circuit design by retrieving the information of the optimum parasitic element of a standard circuit and optimizing the circuit constant considering the optimum parasitic element. CONSTITUTION:Standard circuit data 14 and a parasitic element parameter library 15 of actual measured data 13 of a standard circuit are registered, and by using a net list preparing means, a net list 16 with a standard circuit parasitic element is prepared from the data 14 and the library 15. Simultaneously, the list 16 and the actual measured data 13 are read, a circuit simulator 10 is performed, and the sticking method of the parasitic element in which the result is the closest to the actual measured data 13 is obtained. A parasitic element optimizing means 17 to prepare optimum parasitic element information 18 of the standard circuit is equipped, the means 3 is used and thus, the list 16 is prepared from circuit drawing data 2 to perform the simulation and the information 18, and based on the list 16, the circuit constant is optimized 9.

Conversion of MNA equations to state variable form for nonlinear dynamical circuits

Abstract: State space techniques provide a useful means of analysis for electronic circuit simulation. The authors describe a new method for obtaining the discretised, linearised state equations of nonlinear dynamic circuits using modified nodal analysis (MNA). A computer formulation rule to determine these equations, together with an example of its use, is presented.< >

Design of an analogue subthreshold multiplier suitable for implementing an artificial neural network

Abstract: Describes work undertaken as a final-year undergraduate project and considers the design of an analogue VLSI implementation of the multi-layer perceptron artificial neural network. The network is principally composed of multipliers, and therefore the design effort concentrated on the development of a space-efficient multiplier. The circuit exploits the subthreshold region of operation of a MOSFET and it was necessary to examine in detail the modelling of this region of operation. In the course of the work, design tools made available under the ECAD initiative were used; in particular, the circuit simulator HSPICE was used for parameter extraction, in an unconventional way, to great advantage.