Showing papers on "Electronic circuit simulation published in 1996"

Microelectronic Circuit Design

Abstract: This preview guide presents the first 10 chapters of the our new title by Richard Jaeger: Microelectronic Circuit Design. This cutting edge new text develops a comprehensive understanding of the basic techniques of modern electronic circuit design, analog and digital, discrete and integrated. Digital electronics has evolved to be an extremely important area of circuit design, but it is included almost as an after-thought in the majority of introductory electronics texts. This book presents a much more balanced coverage of analog and digital circuits. The writing integrates the author's extensive industrial backround in precision analog and digital design with his many years of experience in the classroom.

EM-ANN models for microstrip vias and interconnects in dataset circuits

Abstract: A novel approach for accurate and efficient modeling of monolithic microwave/millimeter wave integrated circuit (MMIC) components by using electromagnetically trained artificial neural network (EM-ANN) software modules is presented. Full-wave EM analysis is employed to characterize MMIC components. Structures for simulation are chosen using design of experiments (DOE) methodology. EM-ANN models are then trained using physical parameters as inputs and S-parameters as outputs. Once trained, the EM-ANN models are inserted into a commercial microwave circuit simulator where they provide results approaching the accuracy of the EM simulation tool used for characterization of the MIMIC components without increasing the analysis time significantly. The proposed technique is capable of providing simulation models for MMIC components where models do not exist or are not accurate over the desired region of operation. The approach has been verified by developing models for microstrip vias and interconnects in dataset circuits. A new hybrid (/spl Delta/S) modeling approach which makes use of existing approximate models for components is introduced and shown to be a more efficient method for developing EM-ANN models. An example of using EM-ANN models to optimize the component geometry is included.

Optimal transient simulation of transmission lines

Abstract: This paper presents an attempt to formulate a high-level description of the optimal transmission line simulation method. To formulate the optimal approach, most significant aspects of the problem are identified, and alternative approaches in each of the aspects are analyzed and compared to find the combination that results in the maximum efficiency, accuracy and applicability for the transient analysis of digital circuits. The practical implementation of the optimal method for uniform multiconductor lossy frequency-dependent lines characterized by samples of their responses is outlined. It is shown on an extensive set of runtime data that, based on the optimal approach, the accurate line modeling in a circuit simulator is as efficient as the simple replacement of interconnects with lumped resistors.

Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations

Abstract: A time-domain, non-Monte Carlo method for computer simulation of electrical noise in nonlinear dynamic circuits with arbitrary excitations and arbitrary large-signal waveforms is presented. This time-domain noise simulation method is based on results from the theory of stochastic differential equations. The noise simulation method is general in the following sense. Any nonlinear dynamic circuit with any kind of excitation, which can be simulated by the transient analysis routine in a circuit simulator, can be simulated by our noise simulator in time-domain to produce the noise variances and covariances of circuit variables as a function of time, provided that noise models for the devices in the circuit are available. Noise correlations between circuit variables at different time points can also be calculated. Previous work on computer simulation of noise in electronic circuits is reviewed with comparisons to our method. Shot, thermal, and flicker noise models for integrated-circuit devices, in the context of our time-domain noise simulation method, are discussed. The implementation of this noise simulation method in a circuit simulator (SPICE) is described. Two examples of noise simulation (a CMOS inverter and a BJT active mixer) are given.

A rational formulation of thermal circuit models for electrothermal simulation. I. Finite element method [power electronic systems]

Abstract: As the size of the semiconductor devices is getting smaller with advanced technology, self-heating effects in power semiconductor devices are becoming important. An electrothermal simulation of complete power electronic systems that include Si chips, thermal packages, and heat sinks is essential for an accurate analysis of the behavior of these systems. This paper presents a rational approach to construct thermal circuit networks equivalent to a discretization of the heat equation by the finite element method. Elemental thermal circuit networks are developed, which correspond to the linear and cubic Hermite elements in the 1-D case, to the triangular and rectangular elements in the 2-D case, and to the tetrahedral and cube elements in the 3-D case. These thermal circuit networks are to be connected to the electrical networks of power electronic systems to provide complete electrothermal models that can be conveniently used in any circuit simulator package. Verification examples are presented to demonstrate the accuracy of the proposed formulation.

A rational formulation of thermal circuit models for electrothermal simulation-Part I: Finite element method

Abstract: As the size of the semiconductor devices is getting smaller with advanced technology, self-heating effects in power semiconductor devices are becoming important. An electrother- mal simulation of complete power electronic systems that include Si chips, thermal packages, and heat sinks is essential for an accurate analysis of the behavior of these systems. This paper presents a rational approach to construct thermal circuit net- works equivalent to a discretization of the heat equation by the finite element method. Elemental thermal circuit networks are developed, which correspond to the linear and cubic Hermite elements in the 1-D case, to the triangular and rectangular elements in the 2-D case, and to the tetrahedral and cube elements in the 3-D case. These thermal circuit networks are to be connected to the electrical networks of power electronic systems to provide complete electrothermal models that can be conveniently used in any circuit simulator package. Verification examples are presented to demonstrate the accuracy of the proposed formulation.

Optimization of custom MOS circuits by transistor sizing

Abstract: Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses LANCELOT, a large-scale nonlinear optimization package with an augmented Lagrangian formulation. Simple bounds are handled explicitly and trust region methods are applied to minimize a composite objective function. In the inner loop of the optimization, the fast circuit simulator SPECS is used to evaluate the circuit. SPECS is unique in its ability to efficiently provide time-domain sensitivities, thereby enabling gradient-based optimization. Both the adjoint and direct methods of sensitivity computation have been implemented in SPECS. To assist the user, interfaces in the Cadence and SLED design systems have been constructed. These interfaces automate the specification of the optimization task, the running of the optimizer and the back-annotation of the results on to the circuit schematic. JiffyTune has been used to tune over 100 circuits for a custom, high-performance microprocessor that makes use of dynamic logic circuits. Circuits with over 250 tunable transistors have been successfully optimized. Automatic circuit tuning has been found to facilitate design re-use. The designers' focus shifts from solving the optimization problem to specifying it correctly and completely. This paper describes the algorithms of JiffyTune, the environment in which it is used and presents a case study of the application of JiffyTune to individual circuits of the microprocessor.

Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices

Abstract: In this paper, we present a compact electrothermal device model which can be used to simulate NMOS devices operating in the snapback regime By incorporating temperature dependencies in the device model and using the electrothermal circuit simulator iETSIM, we are able to simulate the second breakdown of NMOS devices under EOS stress The NMOS model also incorporates the finite breakdown time effect which is important for simulating charge device model (CDM) ESD stress events

Hard drive of high power GTOs: better switching capability obtained through improved gate-units

Abstract: The paper presents the dynamic behavior of a standard high power GTO (CSG 3003-45) during turn-on and off switching transients under hard drive conditions. The high power switching device and its gate-unit were modeled and simulated in Spice and ABBPisces (2D device and circuit simulator) and their performances were predicted. A gate-unit capable to handle up to |dI/sub G//dt|=5 kA//spl mu/s was realized and tremendous betterment of device original specifications (as per data-sheet supplied from the producer) were observed during measurements. Very good agreement between simulation and laboratory findings were notified during turn-on and turn-off transients. This is a good indication of homogeneous operation of all 2000 parallel cells of the segmented GTO.

EM-ANN models for via interconnects in microstrip circuits

Abstract: A novel approach for accurate and efficient modeling of MMIC components by using electromagnetically-trained Artificial Neural Network (EM-ANN) software modules is presented. The approach has been verified by developing models for microstrip via and stripline-to-stripline interconnects in multilayer circuits. Implementation of the approach is demonstrated by integrating the EM-ANN models in commercial microwave circuit simulator.

Verification system for circuit simulator

Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier is coupled to the HDL circuit simulator so as to control the HDL circuit simulator's operation, including specifying conditions under which the HDL circuit simulator is to stop simulation of a specified circuit and specifying input signal waveforms to be used by the HDL circuit simulator. The circuit simulation verifier receives signal waveforms generated by the HDL circuit simulator for specified watched signals. The circuit simulation verifier then determines whether predefined logical combinations of the watched signals meet specified operational correctness and/or performance criteria within specified time frames. A test bench is composed of a sequence of instructions, including instructions indicating when to activate various operational correctness and/or performance criteria, instructions for sending commands to the HDL simulator, and branch or condition instructions for controlling which instructions of the test bench are to be executed. Furthermore, a test bench can include instructions for generating a plurality of distinct threads of execution, each of which is composed of its own sequence of instructions, and furthermore can include instructions for conditionally spawning additional threads of execution when specified combinations of Expect Events are satisfied in specified ones of the threads.

A circuit topology for microwave modeling of plastic surface mount packages

Abstract: A circuit topology is described for modeling a class of plastic surface mount packages. The model consists of three pieces each of which is circuit modeled based on an electromagnetic simulation. The resulting parts of the model can then be interconnected with each other and with the model of the monolithic microwave/millimeter wave integrated circuit (MMIC) to be packaged. Various interconnections and grounding schemes can be investigated without resorting to further electromagnetic simulation. The circuit model topology is verified by circuit simulating two simple packaged test circuits and comparing the results to a full electromagnetic simulation. The resulting S parameters are in good agreement over a wide range of frequencies and for a variety of grounding configurations.

Physically based description of quasi-saturation region of vertical DMOS power transistors

Abstract: For short circuit design protection, quasi-saturation behaviour of vertical power DMOS transistors has to be included in circuit simulator compact models. In this region an unexpected increase in current has been observed, due to the injection of electrons from the n/sup +/ source region into the n-substrate. The purpose of this paper is to analyze this effect and include its results in a compact model for circuit simulation.

Neural network applications in device and subcircuit modelling for circuit simulation

Abstract: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

Apparatus and method for verifying the timing performance of critical paths within a circuit using a static timing analyzer and a dynamic timing analyzer

Abstract: A method of improving the timing performance of a circuit includes the step of producing a first set of timing results from a static timing analyzer operating on a netlist that characterizes a circuit. A critical timing path within the circuit is then identified from the first set of timing results. The critical timing path is then converted into an equivalent schematic circuit representation. A simulation of the equivalent schematic circuit representation on a circuit simulator produces a second set of timing results. Timing discrepancies are then located between the first set of timing results and the second set of timing results. Based upon the timing discrepancies, cells are substituted into the critical timing path to improve the timing performance of the critical timing path.

Concurrency preserving partitioning (CPP) for parallel logic simulation

Abstract: Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves circuit concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the concurrency preserving partitioning (CPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases, and three conflicting goals can be separately considered in each phase so to reduce computational complexity. A parallel gate-level circuit simulator is implemented on an Intel Paragon machine to evaluate the performance of the CPP algorithm. The results are compared with two other partitioning algorithms to show that reasonable speedup may be achieved with the algorithm.

Periodic steady-state analysis of an autonomous power electronic system by a modified shooting method

Abstract: This paper proposes a new periodic steady-state analysis method for an autonomous power electronic system by solving a periodic steady-state condition and a switch condition simultaneously for finding initial values. The method utilizes switching operations, which are a characteristic feature of a power electronic circuit, to express a variation of a period. There is no need to include a period T as an unknown variable. This modification eliminates two disadvantages of the conventional method; one is failure of finding solutions due to wrong initial values and the other is that an initial time does not coincide with a starting time of a circuit topological mode.

Symbolic analysis-a tool for teaching undergraduate circuit theory

Abstract: In this paper, we discuss ways in which traditional courses in circuit theory can benefit by having students learn and apply symbolic analysis methods. Examples of applications are given, and currently available software is discussed.

Dynamic analysis of qualitative circuits for failure mode and effects analysis

Abstract: There are a number of reason for wanting to generate FMEAs as soon in the design process as possible; three of the more notable being safety, reliability and cost. The Flame system provides electrical engineers with a means of automating FMEA using, amongst other techniques, qualitative circuit analysis. Until recently, the qualitative circuit simulator with Flame has only been able to generate failure descriptions for circuits containing a set of relatively simple components; for example, bulbs, resistors, connectors, wires and switches. Representing and reasoning about the operation of CPUs, multi-way switches, sensors, multi-speed motors, and other complex components was not possible due to their intricate effect on a circuit. The paper describes how the behaviour of such components and their failure modes can now be represented; and gives an example of analysing a central door locking circuit containing such complex components. The technology which has facilitated such advances is the dynamic analysis of qualitative circuits. This allows the circuit analyser in Flame to represent and reason about dependencies within a circuit; for example, a relay switch state depends on the state of the coil, and ECU output on the state of the inputs. Because of these advances, Flame can now perform FMEAs of large complex circuits-as found in modern automobiles.

CAD-oriented fullwave equivalent circuit models for waveguide components and circuits

Abstract: New multimode equivalent circuit models for single and cascaded E-plane and H-plane step discontinuities in rectangular waveguides are presented. The computer-aided design (CAD)-oriented equivalent circuit models enable rigorous and efficient fullwave analysis of waveguide components and circuits entirely by circuit simulation. The method has been implemented on the microwave circuit simulator Libra and applied to waveguide structures containing single and cascaded irises and stub discontinuities. Comparisons of circuit simulation results for single and cascaded inductive irises as well as a single and three E-plane stubs with the standard mode-matching method show perfect agreement. Results of a Ka-band bandpass filter analysis are in good agreement with a mode-matching solution that includes the correct edge condition.

A new empirical large-signal HEMT model

Abstract: We propose an empirical large-signal model of high electron mobility transistors (HEMTs). The bias-dependent data of small-signal equivalent circuit elements are obtained from S-parameters measured at various bias settings. And C/sub gs/, C/sub gd/, g/sub m/, and g/sub ds/, are described as functions of V/sub gs/ and V/sub ds/. We included our large-signal model in a commercially available circuit simulator as a user-defined model and designed a 30/60-GHz frequency doubler. The fabricated doubler's characteristics agreed well with the design calculations.

Compact non-local modeling of impact ionization in SOI MOSFETs for optimal CMOS device/circuit design

Abstract: A comprehensive but compact non-local model for impact ionization current in scaled SOI MOSFETs is developed. The model, applicable to both fully depleted and non-fully depleted SOI CMOS, is intended for device/circuit simulation and has been implemented as post-processing in a circuit simulator SOISPICE [J. G. Fossum, SOI-SPICE-4 (FD/SOI and NFD/SOI MOSFET Models). University of Florida, Gainesville, FL (March 1995)]. The model is based on transforming the empirical field-dependent impact ionization rate into a carrier temperature-dependent one via a quasi-steady-state approximation of the energy balance equation. The model is valid for weak as well as strong inversion. It is verified via predictions of structure-dependent drain-source breakdown and current kinks in a variety of floating-body SOI MOSFETs. SOISPICE simulations reveal insight into the design optimization of scaled SOI CMOS devices and circuits in which the breakdown, due to the parasitic BJT driven by impact ionization, must be controlled.

Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

Abstract: In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigated.

A systematic technique for verifying critical path delays in a 300 MHz Alpha CPU design using circuit simulation

Abstract: A static timing verifier is an important tool in the design of a complex high performance VLSI chip such as an Alpha CPU. A timing verifier uses a simple and pessimistic delay model to identify critical failing paths in the design, which then need to be fixed. However, the pessimistic delay model results in a large number of correct paths being identified as failing paths, possibly leading to wasted design resources. Therefore, each critical path identified by the timing verifier needs to be analyzed using a circuit simulator such as SPICE in order to confirm that it is a real failure. Setting up such a simulation is complex, especially when the critical path consists of structures appearing in a datapath of the CPU. In this paper, we present algorithms for the construction of a model for simulating the maximum delay through a critical path. This technique has been used to analyze several critical paths during the design of a 300 MHz Alpha CPU.

A bond graph simulator for power train simulation including semiconductor device models

Abstract: The paper present a bond graph-based circuit simulator, called PACTE. PACTE enables the simulation of a complete power train but offering the various representation levels required by the different design aspects (architecture, power semiconductor devices, control loop, thermal modeling...). Particularly the representation levels are presented and a state-of-the-art in power electronic converter simulation is discussed. Limitations of available software are listed and a solution is presented that is implemented in out simulator. The features of PACTE are discussed and illustrated by a significant example (a power train including a 3-phase inverter and an asynchronous motor for automotive applications). The core of the paper is to specify the required tools for achieving the various simulations needs for power trains.

Internal dynamics of IGBT during short circuit switching

Abstract: This paper reports the internal dynamics of IGBT under short circuit switching conditions. Short circuit performance of IGBTs has been studied in detail with the aid of extensive measurements and numerical simulations. An advanced two-dimensional mixed device and circuit simulator has been employed to examine IGBT behaviour under short circuit stress. The self-heating mechanism is incorporated by self-consistently solving heat generation and diffusion equations with semiconductor charge balance and transport equations. A latch-up free punch-through IGBT has been examined. It is shown that hot-spot generation due to current crowding and impact ionization are the causes of breakdown of an IGBT under short circuit switching. Use of a wider gate is likely to improve the ruggedness of the device.

Simulation in power electronics

Abstract: The use of simulation has always been a powerful tool for technology in all its various fields of application. Especially from an economical point of view, it appears to be profitable. Basic mistakes in a system design can be recognized fast and by this fail investments are avoided. The euphory which accompanies such a description must be handled with care. A broad range of simulation program packages is offered to the engineer. Behind each of these programs hide different simulation techniques and topologies. The aim of this paper is to show in which field of application, which kind or simulation methods can be used and how it can be used for simulating power electronic circuits. The following programs were tested on a PC-based network: PSpice 6.2, ICAP/4, KREAN 4.1, CASPOC, SIMPLORER 3.2, SIMSEN, Micro-Cap/V, ELECTRONIC WORKBENCH, and MATLAB-SIMULINK.

Statistical techniques for the computer-aided optimization of analog integrated circuit

Abstract: A CAD tool capable of performing statistical circuit simulation, design, and optimization is described. The core of this tool is a general, CAD-compatible, statistical model which accounts for the effect of device area, transistor bias, and circuit layout on the variation of MOS integrated circuits. The statistical model has been incorporated into an object-oriented circuit simulator, APLAC, which has sufficient flexibility to allow optimization loops within a simulation input deck. The optimization of a two-stage operational amplifier, including the optimization of the standard deviation of the offset voltage, is performed using both steepest descent and constrained optimization techniques as an illustration of this statistical CAD tool. In this example, it is shown that the transistors which cause variations in op-amp circuit performance can be identified and resized in an area-efficient manner to meet a prescribed parametric circuit yield.

Liquid‐crystal display cell model using piecewise approximations

Abstract: The dynamic characteristics of the capacitance of liquid-crystal display (LCD) pixel constituting the active matrix LCD device using amorphous thin film transistors (TFTs) have been analyzed; an electrically equivalent circuit model is proposed based on the obtained results. The model consists of nonlinear resistors and dynamic elements such as capacitors or inductors and can represent the voltage and time dependence of the capacitance value in the LCD pixel. The proposed model is incorporated into the circuit simulator SPICE as a built-in model.

CAD-oriented equivalent circuit models for rigorous full-wave analysis and design of waveguide components and circuits

Abstract: A new multi-mode equivalent circuit model for cascaded waveguide step discontinuities is presented. This CAD-oriented equivalent circuit model enables rigorous and efficient full-wave analysis of waveguide components and circuits entirely by circuit simulation. The method has been implemented on the microwave circuit simulator Libra. Comparisons of circuit simulation results for single and cascaded inductive irises with the standard mode-matching method show perfect agreement. Results of a Ka-band bandpass filter analysis show good agreement with other mode-matching solutions.