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Showing papers on "Electronic circuit simulation published in 1998"


Book
01 Oct 1998
TL;DR: This comprehensive volume reveals how, using basic principles of elementary circuit analysis along with familiar numerical methods, readers can build up sophisticated electronic simulation tools capable of analyzing large, complicated circuits.
Abstract: This comprehensive volume reveals how, using basic principles of elementary circuit analysis along with familiar numerical methods, readers can build up sophisticated electronic simulation tools capable of analyzing large, complicated circuits. The book describes in clear language an especially broad range of uses to which circuit simulation principles may be put-from running general applications, to understand why SPICE works in some cases and not in others.

106 citations


Proceedings ArticleDOI
17 May 1998
TL;DR: In this article, the authors implemented models of power semiconductor devices in the circuit simulator PSpice and obtained high accuracy and validity in a wide operation range due to the derivation from device physics.
Abstract: Models of power semiconductor devices are implemented in the circuit simulator PSpice. The combination of subcircuits and mathematical functions enables very compact solutions. High accuracy and validity in a wide operation range are obtained due to the derivation from device physics. Models of the power diode and the IGBT are presented as examples.

105 citations


Journal ArticleDOI
TL;DR: A circuit optimization tool that automates the tuning task by means of state-of-the-art nonlinear optimization, which makes use of a fast circuit simulator and a general-purpose non linear optimization package and presents extensive circuit optimization results.
Abstract: Automating the transistor and wire-sizing process is an important step toward being able to rapidly design high-performance, custom circuits. This paper presents a circuit optimization tool that automates the tuning task by means of state-of-the-art nonlinear optimization. It makes use of a fast circuit simulator and a general-purpose nonlinear optimization package. It includes minimax and power optimization, simultaneous transistor and wire tuning, general choices of objective functions and constraints, and recovery from nonworking circuits. In addition, the tool makes use of designer-friendly interfaces that automate the specification of the optimization task, the running of the optimizer, and the back-annotation of the results of optimization onto the circuit schematic. Particularly for large circuits, gradient computation is usually the bottleneck in the optimization procedure. In addition to traditional adjoint and direct methods, we use a technique called the adjoint Lagrangian method, which computes all the gradients necessary for one iteration of optimization in a single adjoint analysis. This paper describes the algorithms and the environment in which they are used and presents extensive circuit optimization results. A circuit with 6900 transistors, 4128 tunable transistors, and 60 independent parameters was optimized in about 108 min of CPU time on an IBM RISC/System 6000, model 590.

70 citations


Patent
Atsushi Kasuya1
14 Sep 1998
TL;DR: An electronic circuit verification system and method as mentioned in this paper includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL simulator.
Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier executes a test bench so as to define operational correctness and/or performance criteria, including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation, and a time frame during which the signal value combination is expected to occur. The circuit simulation verifier includes instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation and the time frame expiring.

53 citations


Proceedings ArticleDOI
12 Oct 1998
TL;DR: In this paper, the use of mathematical optimisation routines in connection with general purpose circuit simulators is discussed, and a tool which connects the circuit simulator SABER with optimization routines in MATLAB is developed.
Abstract: This article gives an introduction to optimised design of power electronic circuits. The use of mathematical optimisation routines in connection with general purpose circuit simulators is discussed. A tool which connects the circuit simulator SABER with optimisation routines in MATLAB is developed. A detailed description of the optimisation of a gate-drive for an inverter leg in a frequency converter is given.

51 citations


Journal ArticleDOI
Colin C. McAndrew1
TL;DR: Common-sense guidelines for modeling are detailed and particular emphasis is given on understanding accuracy requirements and numerical requirements, on ensuring that compact models are asymptotically correct, and on highlighting the real goal of modeling for circuit simulation: getting complete models for allowable device layouts working in the CAD system on a designer's desk.
Abstract: There is much more to modeling for circuit simulation than deriving a set of I(V), and perhaps Q(V), equations and extracting a SPICE MODEL card. Unfortunately, some practical aspects of modeling are often overlooked. This paper details common-sense guidelines for modeling and highlights common modeling problems. Particular emphasis is given on understanding accuracy requirements and numerical requirements, on ensuring that compact models are asymptotically correct, and on highlighting the real goal of modeling for circuit simulation: getting complete models for allowable device layouts working in the CAD system on a designer's desk.

47 citations


Journal ArticleDOI
TL;DR: In this paper, the performance of IGBTs under unclamped inductive switching (UIS) and short circuit (SC) conditions was investigated. And the authors showed that self-heating has a significant impact on device characteristics.
Abstract: The performance of 1200 V punchthrough (PT) and nonpunchthrough (NPT) insulated gate bipolar transistors (IGBT's) is studied in detail under unclamped inductive switching (UIS) and short circuit (SC) conditions. The need for a good physics based simulator to carry out a reliability study is pointed out in the paper. Using such a finite element-based device and circuit simulator it is shown that NPT-IGBT's show a much better performance than PT-IGBTs under UIS condition. It is also shown that an NPT device has a better short circuit withstanding capability than a PT device due to the structural differences between the two devices. As there is a huge power loss within the device during these operating conditions, device self-heating is expected to have a significant impact on device characteristics. Electrothermal simulations are used to study device self-heating and it is shown that it significantly influences device performance under SC operation whereas self-heating influences the UIS performance of only the PT device with little effect on the NPT device. The study is validated by an experimental study of short circuit failure of PT IGBTs.

41 citations


Proceedings ArticleDOI
18 May 1998
TL;DR: In this paper, a lumped component equivalent circuit has been developed to model the linear electrical behavior of any two-winding transformer and its topology is independent of sizes and technology and a general method of characterization based exclusively on external impedance measurements has been presented.
Abstract: A lumped component equivalent circuit has been developed by our team to model the linear electrical behaviour of any two winding transformer. Its topology is independent of sizes and technology and a general method of characterization, based exclusively on external impedance measurements, has been presented. Unfortunately, when some key frequencies are out of the range of the measuring apparatus, many of its components remain unevaluated. Owing to a new understanding of magnetic and electrostatic coupling, a several step approach is presented. At each step a more accurate circuit proven to be effective in electronic simulation, is fully characterized. This method suits whatever the number of windings and experimental data will be presented for two and three winding transformers.

39 citations


Patent
04 May 1998
TL;DR: In this article, a method for power net analysis of integrated circuits is provided, where a circuit simulator determines current values for integrated circuit devices at specified supply voltages, and a power net simulator uses the current values to calculate characteristics of the power net.
Abstract: A method for power net analysis of integrated circuits is provided. A circuit simulator determines current values for integrated circuit devices at specified supply voltages. A power net simulator uses the current values to calculate characteristics of the power net. The characteristics include voltage drop, current density and ground bounce. A layout representation of the power net is shown on a computer display along with the user-specified characteristics.

38 citations


Proceedings ArticleDOI
23 Feb 1998
TL;DR: SyMPVL is introduced, an algorithm for the approximation of the symmetric multi-port transfer function of an RLC circuit that employs a symmetric block-Lanczos algorithm to reduce the original circuit matrices to a pair of typically much smaller, banded, symmetric matrices.
Abstract: This paper introduces SyMPVL, an algorithm for the approximation of the symmetric multi-port transfer function of an RLC circuit. The algorithm employs a symmetric block-Lanczos algorithm to reduce the original circuit matrices to a pair of typically much smaller, banded, symmetric matrices. These matrices determine a matrix-Pade approximation of the multi-port transfer function, and can serve as a reduced-order model of the original circuit. They can be ``stamped'' directly into the Jacobian matrix of a SPICE-type circuit simulator, or can be used to synthesize an equivalent smaller circuit. We also prove stability and passivity of the reduced-order models in the RL, RC, and LC special cases, and report numerical results for SyMPVL applied to example circuits.

36 citations


Patent
Amir M. Zarkesh1, Haizhou Chen1
27 Mar 1998
TL;DR: In this article, a power dissipation value is calculated for each transition or event generated during the electronic simulation of an electronic circuit design that corresponds to an actual electronic circuit, which relies on data that includes a cell library having a power model corresponding to a cell instance; cell activity data such as net transitions; and the total effective load seen by each cell pin of the logic cell to be evaluated for power.
Abstract: The present invention evaluates the power dissipation of an electronic circuit. A power dissipation value is calculated for each transition or event generated during the electronic simulation of an electronic circuit design that corresponds to an actual electronic circuit. The present invention relies on data that includes an electronic circuit design description of the electronic circuit, such as a gate level netlist; a cell library having a power model corresponding to a cell instance; cell activity data such as net transitions; and the total effective load seen by each cell pin of the logic cell to be evaluated for power. The power model includes simple arcs (transition delay values, energy per arc values, cell input capacitances, and output slew rate values) and power evaluation data. The total energy dissipated by the cell during the modeled activity is calculated by determining the number of simple arcs applicable to the cell, attributing an energy dissipated for each arc, adding the energy values, and compensating for any double counting of short circuit and internal charge/discharge energy. Two fix-width queues are used by system as directed by the software code in the power evaluation tool. A queue may be defined in memory under program control but may be of any structure either in software or hardware. For each cell instance, power evaluation tool uses a first queue to track every transition and direction of the transition that occurs at an input pin, while a second queue is used to track every transition and direction of the transition that occurs at a boundary pin (i.e., an input pin or at an output pin). A power value for the cell instance may then also be obtained from the total energy dissipated during the modeled activity.

Dissertation
01 Jan 1998
TL;DR: A method of nonuniformly discretizing planar structures is developed which allows for hierarchical descriptions and modification while still enforcing current conservation and the numerically robust Arnoldi approach for efficiently generating compact, or reduced order models for the inductance problem is proposed.
Abstract: As VLSI circuit speeds have increased, the need for accurate three-dimensional interconnect models has become essential to accurate chip and system design. Many of these interconnect structures are small compared to a wavelength, and much work has been directed at rapidly solving for the inductance and capacitance of these structures. The first part of this thesis involves further development of efficient inductance extraction and simulation. First, a method of nonuniformly discretizing planar structures is developed which allows for hierarchical descriptions and modification while still enforcing current conservation. Also, a possible alternate preconditioner to accelerate the iterative method is described. Finally, the most significant contribution for this part is the numerically robust Arnoldi approach for efficiently generating compact, or reduced order models for the inductance problem. Even though much work has been directed toward solving separately for the inductance and capacitance of these structures, these two quantities are not necessarily decoupled, and for higher frequencies a distributed model is necessary. The second part of this thesis develops fast algorithms for solving this full quasistatic Maxwell's equations to effectively capture this "coupled" or distributed capacitance and inductance. The technique employed for extraction is an integral equation approach for modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling along conductors. While such computations by themselves and not new, a technique is proposed for which it is possible to generate guaranteed passive reduced order models for efficient inclusion in a circuit simulator such as SPICE. In their basic form, these methods require direct LU factorization of very large linear systems. Such factorization is impractical due to the $O(n\sp3)$ computation time and $O(n\sp2)$ storage costs. Iterative techniques are then applied which can exploit fast potential solvers such as the Fast Multipole method to bring the cost of model generation to O(n) operations and storage. For a modest problem size, the iterative methods show nearly 2 orders of magnitude speed up in computation time and an order of magnitude less memory than direct factorization. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

Proceedings ArticleDOI
06 Oct 1998
TL;DR: In this article, the authors used circuit simulations in understanding of the internal ESD (electrostatic discharge) failure observed in a 06 /spl mu/m CMOS technology product chip simulation of the ESD current paths near the V/sub dd/pin are performed and the cause of ESD failure is identified using a circuit simulator that includes the MOS snapback models.
Abstract: This paper presents the use of circuit simulations in understanding of the internal ESD (electrostatic discharge) failure observed in a 06 /spl mu/m CMOS technology product chip Simulation of the ESD current paths near the V/sub dd/ pin are performed and the cause of ESD failure is identified using a circuit simulator that includes the MOS snapback models These simulations are used to suggest issues to be considered in design of protection circuits to avoid this type of internal ESD failure

Proceedings ArticleDOI
K. Rahmat1, J. Neves1, J.-F. Lee1
05 Oct 1998
TL;DR: It is shown that a lumped model is quite accurate for predicting noise on a variety of wire geometries up to 3 mm in length, and a technique to extend this model to the practically important case when bus wires overlap only partially with neighbors is proposed.
Abstract: In this paper we compare different methods for calculating coupling noise, specially for use in the early design phase of a high performance custom design when all the detailed physical design information is not available. This analysis can be important in the design of functional blocks such as data paths in microprocessors, where if noise avoidance is included in the design planning phase, later changes in the design may be avoided. Thus, reducing the number of design iterations and overall design time. The ideal noise calculation technique should be very fast and reasonably accurate so as to account for all significant parameters that will affect the noise. We consider three different techniques and compare them with an exact analysis using a circuit simulator. It is shown that a lumped model is quite accurate for predicting noise on a variety of wire geometries up to 3 mm in length. We also propose a technique to extend this model to the practically important case when bus wires overlap only partially with neighbors.

Journal ArticleDOI
TL;DR: In this paper, a test circuit topology is proposed which offers several advantages over existing test circuits, such as the ability to characterize high-power ultrafast rectifiers at very high di/dt and also provides independent control of bias current, reverse voltage and di/d.
Abstract: As circuit switching frequency continues to increase, there is a need to produce faster rectifiers with lower power losses. Efficient utilization of high-power ultrafast rectifiers requires precise knowledge of the key static and dynamic switching parameters, especially the reverse-recovery characteristics. Conventional reverse-recovery test circuits were developed to test rectifiers with reverse-recovery times (t/sub RR/) greater than 100 ns, however, new measurement techniques are needed for accurate characterization and modeling of the high-power ultrafast rectifier reverse-recovery process. A test circuit topology is proposed which offers several advantages over existing test circuits. This circuit offers the ability to characterize high-power ultrafast rectifiers at very high di/dt and also provides independent control of bias current, reverse voltage and di/dt. This circuit is also studied using a two-dimensional (2-D) mixed device and circuit simulator in which the device under test is represented as a 2-D finite-element grid and the semiconductor equations are solved under boundary conditions imposed by the proposed test circuit. This simulation tool is used to understand the device physics of the reverse-recovery process and develop more accurate models to be implemented in behavioral circuit simulators. The simulation results are then compared to the measured data for a silicon P-i-N and 200-V GaAs Schottky rectifier under various measurement conditions. Simulation results are shown to be in excellent agreement with the measured data.

Journal ArticleDOI
TL;DR: In this paper, an electromagnetic three-dimensional (3-D) software is applied to characterize the distributed part of the structure of a microwave device and coupled to a circuit simulator to introduce the contribution on the electrical response of the localized passive or active elements contained in the device.
Abstract: This letter presents a technique to analyze complex microwave devices. An electromagnetic three-dimensional (3-D) software is applied to characterize the distributed part of the structure. It is coupled to a circuit simulator to introduce the contribution on the electrical response of the localized passive or active elements contained in the device. The link between the two parts is made thanks to a new type of access, "the localized access". We have applied this method to the study of a field effect transistor and good agreements are observed between simulations and measurements from 1 to 30 GHz.

Journal ArticleDOI
TL;DR: It is shown that for nonuniform lines, the generalized method of characteristics no longer separates forward and backward waves, and an open-loop distributed-reflection model explicitly includes the internal distributed reflections, and provides the simplest stable characterization.
Abstract: This paper extends the transmission-line simulation method presented previously by Kuznetsov and Schutt-Aint (see IEEE Trans. Circuits Syst. I, vol. 43, p. 111-121, Feb. 1996) to nonuniform lines. The method is applicable to multiconductor lossy frequency-dependent transmission lines characterized by sampled frequency-domain responses. The resulting model can be directly incorporated into a circuit simulator. The implementation includes AC, DC, and transient analyses. The method is reliable, accurate, and as efficient as the simple replacement of interconnects by lumped resistors. The method is based on approximation, and its accuracy and efficiency result from the simplicity of characteristic responses. To apply the method to nonuniform lines, two novel nonuniform line models are introduced. An open-loop model completely separates forward and backward waves and results in the simplest aperiodic responses, but does not guarantee their stability. An open-loop distributed-reflection model explicitly includes the internal distributed reflections, and provides the simplest stable characterization. It is shown that for nonuniform lines, the generalized method of characteristics no longer separates forward and backward waves. Numerical example of a parabolically tapered frequency-dependent four-conductor line is given.


Journal ArticleDOI
TL;DR: In this paper, an event-driven algorithm and its symbolic implementation for the analysis of power and ground (P/G) bus networks is presented, which uses frequency-domain techniques and moment matching approaches based on Pade approximants to estimate the transfer function at each node in the P/G network.
Abstract: This paper presents an event-driven algorithm and its symbolic implementation for the analysis of power and ground (P/G) bus networks. The algorithm uses frequency-domain techniques and moment matching approaches based on Pade approximants to estimate the transfer function at each node in the P/G network. Afterwards, the transient waveforms are extracted for each node. The process requires repetitive simulation of a linear and time-variant (from one time event to the next) circuit model for the P/G network which is the reason a symbolic implementation was produced. The P/G network is modeled by a hierarchical combination of mesh and tree structures that are composed of a collection of RC-/spl pi/-segments and pulldown (or pullup) switches. The switches are symbolically represented by Boolean variables and a compiled symbolic code is generated only once for each P/G network. The transient waveforms are then produced by repetitive evaluation of the symbolic output. The results show that the symbolic implementation is an order of magnitude faster, with reasonably good accuracy, than using a traditional analog circuit simulator like SPICE.

Journal ArticleDOI
TL;DR: In this paper, two types of single-electron simulators have been developed, one for lower level circuit simulation and the other for higher level simulation, denoted as single electron transistor-simulation program with integrated circuit emphasis (SET-SPICE).
Abstract: We have developed two types of single-electron simulators. One is for lower level circuit simulation, denoted as extended single-electron simulator (ESS) and the other is for higher level simulation, denoted as single electron transistor-simulation program with integrated circuit emphasis (SET-SPICE). ESS simulates small-scale arbitrary circuits with precision, performs efficient steady-state analysis besides conventional transient analysis, and visualizes probability distributions. SET-SPICE, on the other hand, simulates large-scale single-electron-transistor circuits with relatively large node capacitances at high speed and performs co-simulation of single electron transistor (SET) and complementary metal oxide semiconductor (CMOS) circuits.

Journal ArticleDOI
TL;DR: In this paper, the authors present a technique for the high speed, accurate, predictive modeling of arbitrary geometry integrated resistor structures manufactured in a variety of technologies, including those of both multichip modules (MCM's) and integrated circuits (IC's).
Abstract: A novel technique is presented for the high speed, accurate, predictive modeling of arbitrary geometry integrated resistor structures manufactured in a variety of technologies, including those of both multichip modules (MCM's) and integrated circuits (IC's). The technique is based upon generating test structures in the process of interest, performing measurements, and extracting the behavior of a few key well identified building blocks. These building blocks can then be used for generating circuit models of other any structure created by valid combinations of those building blocks, which can then be simulated in a standard circuit simulator to predict behavior. The procedure has been experimentally verified, and shows good agreement with actual measurements up to 5-10 GHz. In addition, the model validity has been tested in several circuits by comparing the model predicted results against results obtained using the HP MDS simulator which uses measured parameters directly, with very good results. Since lumped element circuits are generated by this method, structure prediction speed is determined by circuit size and simulator small signal analysis time. The method is versatile and is well suited for circuit design applications.

Proceedings ArticleDOI
23 Feb 1998
TL;DR: A new approach to model the behaviour of nonlinear functional blocks is proposed, based upon the principles of systems theory, that supports the mapping of models from component into behavioural level.
Abstract: Analog simulation methodologies for the generation of macromodels of analog functional blocks, as reported in literature, are of limited use in practical circuit simulation due to frequent accuracy and efficiency problems. In this paper, a new approach to model the behaviour of nonlinear functional blocks is proposed. The approach is based upon the principles of systems theory. The outlined methodology supports the mapping of models from component into behavioural level. The nonlinearity of complex analog modules is reflected efficiently while the electrical signals are maintained.

Proceedings ArticleDOI
10 Aug 1998
TL;DR: A new high speed and low power SOI inverter that can operate with efficient body-bias control and free supply voltage and is shown to have excellent characteristics.
Abstract: We propose a new high speed and low power SOI inverter that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5 V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

Proceedings ArticleDOI
27 Sep 1998
TL;DR: For accurate modeling the transit time of "true" SiGe HBTs up to high current densities, analytical equations have been derived and verified by both device simulations and measurements as mentioned in this paper.
Abstract: For accurate modeling the transit time of "true" SiGe HBTs up to high current densities, analytical equations have been derived and verified by both device simulations and measurements. They are part of a new compact model, which has just been implemented into a commercial circuit simulator.

Proceedings ArticleDOI
19 Jul 1998
TL;DR: An option available in PSpice, called analog behavioral modeling, is used, and mathematical models for any kind of application may be converted into electrical circuits, solved as subcircuit-models with the circuit simulator PSpICE and further graphically evaluated with the postprocessor Probe.
Abstract: Some methods for the implementation of mathematical models of power devices for circuit simulation in the PSpice program are presented. For this purpose, an option available in PSpice, called analog behavioral modeling, is used. In this way, mathematical models for any kind of application may be converted into electrical circuits, solved as subcircuit-models with the circuit simulator PSpice and further graphically evaluated with the postprocessor Probe. The developed procedures are demonstrated with the implementation of a physics-based IGBT model.

Proceedings ArticleDOI
24 Nov 1998
TL;DR: In this paper, an effective procedure for initial hand calculation is given, based upon simulation models and parameters, for manipulating the weakly inverted MOSFET, which can be used in very low power applications.
Abstract: The availability today of process technologies such as submicron CMOS and BiCMOS allow circuit designers to push the limits of circuit performance. However, this is only possible when designers are fully equipped with good understanding of such device operation. In very low power applications, the use of MOSFETs operating in the weak inversion region is very attractive. Nevertheless, it is not easy to manipulate the devices since models such as the BSIM empirical model are complicated and involve too many parameters. As a result, hand calculation for an initial design is very difficult and can be a major obstacle for circuit designers. This paper presents an intuitive way of manipulating the weakly inverted MOSFET. An effective procedure for initial hand calculation is given, based upon simulation models and parameters. Comparisons between the calculation results and simulation results are performed to confirm the concept.

Proceedings ArticleDOI
12 Oct 1998
TL;DR: An option available in PSpice, called analog behavioral modeling, is used, and mathematical models for any kind of application may be converted into electrical circuits, solved as subcircuit-models with the circuit simulator PSpICE and further graphically evaluated with the postprocessor Probe.
Abstract: Some methods for the implementation of mathematical models of power devices for circuit simulation in the PSpice program are presented. For this purpose, an option available in PSpice, called analog behavioral modeling, is used. In this way, mathematical models for any kind of application may be converted into electrical circuits, solved as subcircuit-models with the circuit simulator PSpice and further graphically evaluated with the postprocessor Probe. The developed procedures are demonstrated with the implementation of a physics-based IGBT model.

Journal ArticleDOI
TL;DR: This paper employs fast frequency-sweep methods, such as Asymptotic Waveform Evaluation (AWE) or the Lanczos-based ALPS procedure, to determine the frequency response of an electromagnetic system over a broad frequency band.
Abstract: This paper presents an efficient method for the computation of electromagnetic transients. We employ fast frequency-sweep methods, such as Asymptotic Waveform Evaluation (AWE) or the Lanczos-based ALPS procedure, to determine the frequency response of an electromagnetic system over a broad frequency band. Using a rational function fitting procedure, we compute a reduced-order model of the system's port parameters. Next, an equivalent circuit model is formed. A circuit simulator such as SPICE can then be used to compute the transient response of the system in conjunction with nonlinear driver and load devices. We provide examples to demonstrate the accuracy and efficiency of this technique.

Proceedings ArticleDOI
23 Feb 1998
TL;DR: This paper describes an integral equation approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling along conductors.
Abstract: As VLSI circuit speeds have increased, the need for accurate three-dimensional interconnect models has become essential to accurate chip and system design. In this paper we describe an integral equation approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling along conductors. Unlike previous methods, our approach is based on a modified nodal analysis formulation and can be used directly to generate guaranteed passive low order interconnect models for efficient inclusion in a standard circuit simulator.

Proceedings ArticleDOI
15 Feb 1998
TL;DR: In this article, the performance of IGBTs under short circuit and clamped inductive load conditions has been studied in detail with the aid of extensive measurements and numerical simulations, and it is shown that thermally assisted avalanche breakdown of the IGBT under the two stress conditions occurs due to localized high temperature generation in different regions of the device.
Abstract: This paper reports and compares the internal dynamics of IGBT under short circuit and clamped inductive switching stress. The performance of IGBTs under short circuit and clamped inductive load conditions has been studied in detail with the aid of extensive measurements and numerical simulations. An advanced mixed device and circuit simulator is employed to study the internal dynamics of latch-up free punch-through IGBT. It is shown that thermally assisted avalanche breakdown of IGBT under the two stress conditions occurs due to localized high temperature generation in different regions of the device.