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Showing papers on "Electronic circuit simulation published in 2000"


Proceedings ArticleDOI
S.G. Duvall1
10 Jun 2000
TL;DR: This tutorial reviews statistical circuit modeling and optimization and its applications in integrated circuit design and discusses the main techniques used for statistical modeling, analysis and optimization.
Abstract: This tutorial reviews statistical circuit modeling and optimization and its applications in integrated circuit design. Motivated by a discussion of the importance of statistical design techniques, it introduces the primary concepts and discusses the main techniques used for statistical modeling, analysis and optimization. It also considers some of the important open questions.

92 citations


Journal ArticleDOI
TL;DR: In this article, a numerical simulator for Schottky varactor diode frequency multipliers for millimeter and submillimeter wavelengths is integrated into a circuit simulator to avoid the need of equivalent circuits.
Abstract: Design and optimization of Schottky varactor diode frequency multipliers for millimeter and submillimeter wavelengths are generally performed using harmonic balance techniques together with equivalent-circuit models. Using this approach, it is difficult to design and optimize the device and multiplier circuit simultaneously. The work presented in this paper avoids the need of equivalent circuits by integrating a numerical simulator for Schottky diodes into a circuit simulator. The good agreement between the calculated and published experimental data for the output power and conversion efficiency originates from the accurate physical model. The limiting effects of multiplier performance such as breakdown, forward conduction, or saturation velocity are discussed in view of the optimum circuit conditions for multiplier operation including bias point, input power, and loads at different harmonics. It is shown that the onset of forward or reverse current flow is responsible for the limitation in the conversion efficiency.

78 citations


Journal ArticleDOI
TL;DR: The concept of Integrated Power Modules (IPMs) was introduced in this article, in which the electronic control circuitry and the high power electronics of the converter are integrated into a single compact standardized module.

77 citations


Journal ArticleDOI
TL;DR: A new methodology for generating transient tests to detect faults in analog circuits is presented and it is found to give low misclassification rates for a large class of analog circuits.
Abstract: In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits.

67 citations


Journal ArticleDOI
TL;DR: In this paper, an electrothermal model of the IGBT has been developed for the prediction of IGBT failure phases in the case of large surges, where the reason of the device destruction is a thermal runaway, and the model has been optimized to give a good tradeoff between accuracy and simulation cost.
Abstract: This paper discusses the possible estimation of IGBT failure phenomena by means of simulation. The studied destruction mode addresses the large surges, especially the short-circuit of IGBTs. In this case the reason of the device destruction is a thermal runaway. Thus we have developed an electrothermal model of the IGBT. The developed model may be implemented in any circuit simulator featuring a high level description language (SABER, ELDO, SMASH, PACTE etc.). The used electrical model is based on the Hefner model of the IGBT. A bidimensional finite element thermal model is considered. This model has been optimized to give a good trade-off between accuracy and simulation cost. To validate the implemented model, finite element simulations have been performed with the ATLAS two-dimensional (2-D) numerical simulator. The study is completed with the comparison between experimental and simulation results. It is shown that the proposed electrothermal model allows the prediction of the IGBT destruction phases in the case of large surges. So, users of IGBT components have the possibility to estimate, by mean of simulation, the possible failure (due to large surges) of these devices in the case of complex converters. This enables the possibility for developing protection systems for IGBTs without any destructive test.

53 citations


Patent
30 Nov 2000
TL;DR: In this article, the authors apply genetic algorithmic generation of test cases for the simulation of VLSI logic circuit blocks, where the results of the simulator are maintained in a matrix or table.
Abstract: The present invention applies genetic algorithmic generation of test cases the simulation of VLSI logic circuit blocks. The present invention generates a number of original test cases. This aggregate of solutions is provided to a circuit simulator. The results of the simulator are maintained in a matrix or table. The results detail the number of times that particular logic states or events associated with the VLSI block have been stimulated by particular test cases. The aggregate of solutions and the simulation results are then analyzed by the genetic algorithm. The genetic algorithm preferably identifies states associated with the circuit simulation that have not been produced by the original test cases. The genetic algorithm then combines characteristics of various test cases to generate new test cases. The new test cases are provided to the circuit simulator thereby providing a higher degree of confidence that the entire VLSI chip design has been simulated.

49 citations


Journal ArticleDOI
TL;DR: In this paper, a new macromodeling algorithm for time domain simulation of interconnects is presented, which incorporates Householder LS curve-fitting techniques and enables simulation of the interconnect in a modified version of simulation program with integrated circuit emphasis.
Abstract: As digital circuits approach the GHz range, and as the need for high performance wireless devices increases, new simulation tools which accurately characterize high frequency interconnects are needed. In this paper, a new macromodeling algorithm for time domain simulation of interconnects is presented. The algorithm incorporates Householder LS curve-fitting techniques. The approach generates a universal macromodeling tool that enables simulation of interconnects in a modified version of simulation program with integrated circuit emphasis (SPICE). This results in a method that conveniently incorporates accurate EM models of interconnects or experimental data into a circuit simulator. The time domain simulation results using this new tool are compared with results from other simulators.

49 citations


Journal ArticleDOI
TL;DR: This work describes a synthesis system that takes operating range constraints and inter and intracircuit parametric manufacturing variations into account while designing a sized and biased analog circuit, and shows that it leads to better starting points for post-synthesis yield optimization than a classical nominal synthesis approach.
Abstract: We describe a synthesis system that takes operating range constraints and inter and intracircuit parametric manufacturing variations into account while designing a sized and biased analog circuit. Previous approaches to computer-aided design for analog circuit synthesis have concentrated on nominal analog circuit design, and subsequent optimization of these circuits for statistical fluctuations and operating point ranges. Our approach simultaneously synthesizes and optimizes for operating and manufacturing variations by mapping the circuit design problem into an infinite programming problem and solving it using an annealing within annealing formulation. We present circuits designed by this integrated synthesis system, and show that they indeed meet their operating range and parametric manufacturing constraints. And finally, we show that our consideration of variations during the initial optimization-based circuit synthesis leads to better starting points for post-synthesis yield optimization than a classical nominal synthesis approach.

45 citations


Proceedings ArticleDOI
26 Sep 2000
TL;DR: A new tool is introduced which automatically reduces the number of voltage nodes per ESD simulation by including only those devices that are necessary, and a simple method for modeling ESD device failure while maintaining compatibility with existing CAD tools and libraries is discussed.
Abstract: For many classes of technologies and circuits, it is beneficial to perform circuit simulations for ESD design, verification, and performance prediction. This is particularly true for mixed-signal ICs, where complex interaction between I/Os and multiple power supplies make manual analysis difficult and error prone. Unfortunately, high node and component counts typically prohibit simulations of an entire circuit. Thus, a manual intervention by the designer is usually required to minimize the circuit size. This paper introduces a new tool which automatically reduces the number of voltage nodes per ESD simulation by including only those devices that are necessary. In addition, a simple method for modeling ESD device failure while maintaining compatibility with existing CAD tools and libraries is discussed.

41 citations


Proceedings ArticleDOI
05 Nov 2000
TL;DR: A high accuracy system for transistor-level static timing analysis that takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate.
Abstract: A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor level circuit simulator allows efficient invocation of the simulation.

33 citations


Proceedings ArticleDOI
28 May 2000
TL;DR: A new algorithm is proposed by combining the Arnoldi method and Taylor series expansion for carrying out model-order reduction on quadratic or even higher order nonlinear systems.
Abstract: In this paper, we apply the Arnoldi method to generate accurate reduced-order models for coupled energy domain nonlinear microelectromechanical devices. Besides the traditional application of Arnoldi method to generate reduced-order models for linear systems, we propose a new algorithm by combining the Arnoldi method and Taylor series expansion for carrying out model-order reduction on quadratic or even higher order nonlinear systems. A well-known nonlinear MEMS device, electrostatic actuated fixed-fixed beam device with squeeze-film damping effect, is studied. Simulation results demonstrate that the reduced nonlinear model has a much better accuracy to capture the original device behavior than the simple linearization method. The reduced MEMS device model can be easily connected to a circuit simulator for efficient system level simulations.

Journal ArticleDOI
TL;DR: In this paper, a simple but accurate simultaneous switching-noise (SSN) model for complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) package design was developed.
Abstract: A new simple but accurate simultaneous-switching-noise (SSN) model for complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) package design was developed. Since the model is based on the sub-micron metal-oxide-semiconductor (MOS) device model, it can predict the SSN for today's sub-micron-based very large scale integration (VLSI) circuits. In order to derive the SSN model, the ground path current is determined by taking into account all the circuit components such as the transistor resistance, lead inductance, load capacitance, and oscillation frequency of the noise signal. Since the current slew rate is not constant during the device switching, a rigorous analysis to determine the current slew rate was performed. Then a new simple but accurate closed-form SSN model was developed by accurately determining current slew rate for SSN with the alpha-power-law of a sub-micron transistor drain current. The derived SSN model implicitly includes all the critical circuit performance and package parameters. The model is verified with the general-purpose circuit simulator, HSPICE. The model shows an excellent agreement with simulation even in the worst case (i.e., within a 10% margin of error but normally within a 5% margin of error). A package design methodology is presented by using the developed model.

Journal ArticleDOI
TL;DR: In this paper, the authors describe how, when circuit and device designers jointly tailor power electronics systems to a specific application, performance and reliability can benefit at little or no cost, at the expense of cost.
Abstract: The author describes how, when circuit and device designers jointly tailor power electronics systems to a specific application, performance and reliability can benefit at little or no cost.

Journal ArticleDOI
TL;DR: In this article, the modified method of characteristics (MMC) is presented to analyze lossy interconnects, which applies lower-order Taylor approximation to model the characteristic admittance, and further applies lower order Pade approximation to modeling propagation functions of a transmission line.
Abstract: In this paper, the modified method of characteristics (MMC) is presented to analyze lossy interconnects. The method applies lower order Taylor approximation to model the characteristic admittance, and further applies lower order Pade approximation to model propagation functions of a transmission line. However, different from the single-point or multipoint moment-matching approaches, this method does not generate a reduced-order model of a transmission line prior to constructing the system matrix. Instead, it takes a special expansion and directly incorporates the coefficients of the expansion into the modified nodal admittance (MNA) matrix. On the basis of the specific expansion, a set of time-domain recursive formulae is derived, which concerns only the quantities at the ends of transmission lines. The recursive formulae are similar to those of method of characteristics (MC), with some added modifications. Based on the formulae of MMC, an equivalent time-domain macromodel of a uniform lossy transmission line is obtained. It can be easily implemented within the framework of an existing circuit simulator such as SPICE. The examples indicate that the method gives accurate time-domain simulation of interconnects in high-speed IC systems.

Journal ArticleDOI
TL;DR: In this paper, an analytic model for the I-V characteristics of a single-electron transistor, which may be incorporated in a conventional circuit simulator, such as SPICE, is presented.

Proceedings Article
01 Feb 2000
TL;DR: A parallel GA and its use in automated high-level circuit design and discussion of one such circuit-construction programming language and how evolution can generate useful analog circuit designs are discussed.
Abstract: Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Patent
28 Apr 2000
TL;DR: In this article, an EDA tool is provided with a circuit simulator that simulates circuit operation using dynamic partitioning and on-demand evaluation, which includes a static partitioner, a dynamic partitioner and an evaluation scheduler.
Abstract: An EDA tool is provided with a circuit simulator that simulates circuit operation using dynamic partitioning and on-demand evaluation. The circuit simulator includes a static partitioner, a dynamic partitioner and an evaluation scheduler. The static partitioner pre-forms a number of static partitions for the circuit. During simulation, the dynamic partitioner forms and re-forms a number of dynamic partitions referencing the static partitions. At each simulation time step, the evaluation scheduler determines which, if any, of the dynamic partitions have to be evaluated, and evaluating on-demand only those where evaluations are necessary. In one embodiment, when evaluations are performed, they are performed through matrix solution when accuracy is needed.

Patent
16 Aug 2000
TL;DR: A battery model for circuit simulation is presented in this paper, which comprises a transmission line type network consisting of a non-standard particle that represents physical properties, chemical properties, ionic and atomic transport properties, charge and discharge rates, temperature and history of usage of rechargeable cells.
Abstract: A battery model for circuit simulation is provided. The battery model comprises a transmission line type network. The network includes a non-standard particle that represents physical properties, chemical properties, ionic and atomic transport properties, charge and discharge rates, temperature and history of usage of rechargeable cells. The model can be represented as a graphical icon within the circuit simulator. The model allows accurate representation of battery cells. The model is a modularized mathematical model that can be programmed using a circuit simulator's structure and language. This invention breaks the continuous mathematical model into pieces that are digestible by common circuit simulators.

Journal ArticleDOI
TL;DR: In this article, a circuit simulator in the transient mode can predict circuit aging using a transformation of the dc/ac biasing situation with an appropriate scaling mechanism, based on measurements and empirical modeling.

Journal ArticleDOI
TL;DR: PREDICTMOS-a predictive compact model for structure oriented simulation of MOS devices is presented which has been developed by use of strongly physics-based model equations for threshold voltage, surface potential in weak inversion, and currents in strong inversion including the saturation regime.
Abstract: In circuit design and device scaling investigations, there is still a demand for improved analytical models of MOSFETs with less fitting parameters and a good scalability. In this paper, PREDICTMOS-a predictive compact model for structure oriented simulation of MOS devices is presented which has been developed by use of strongly physics-based model equations. For threshold voltage, surface potential in weak inversion, and currents in strong inversion including the saturation regime, the equations have been derived using our recently published conformal mapping techniques for solving the two-dimensional Poisson equation, and a new way to solve the transistor current differential equation. They make use of real structural parameters without any need of physically meaningless fitting parameters. This results in a strong link between electrical parameters and the process and layout data of the device and an excellent scalability while keeping physical insight. PREDICTMOS has been implemented in the ELDO circuit simulator. Its results in comparison with numerical device simulations and measurements show good agreement down to dimensions of 0.1 μm .


Proceedings ArticleDOI
01 Jan 2000
TL;DR: In this article, the authors used harmonic analysis and simplified antenna models to calculate radiated EMI emission levels of high frequency switched-mode power converters and used a generic circuit simulator for preliminary EMC design.
Abstract: This paper concerns prediction of radiated EMI of high frequency switched-mode power converters. Harmonic analysis and simplified antenna models are used to calculate radiated EMI emission levels. Characteristics of radiated EMI from power converters are presented. The EMI bound of a power converter can be estimated. Quantitative comparison of EMI levels of converters with identical geometrical layout can be made. The validity of this method is analysed. The proposed method enables radiated EMI from high frequency power converters to be predicted using a generic circuit simulator, providing a useful method for preliminary EMC design.

Patent
31 Jul 2000
TL;DR: In this article, the authors present a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals.
Abstract: Described herein is a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals by exhibiting a consequent behavior of producing a particular pattern in its output signals during a finite time following the antecedent event. The system includes a conventional circuit simulator for simulating the behavior of the circuit under conditions defined by a user-provided test bench. The simulator produces output waveform data representing the behavior of the circuit input, output and internal signals, including signals representing the circuit's state. When the output waveform data indicates the antecedent event has occurred, the system determines the current state of the circuit from the waveform data. The system then creates and analyzes a temporally expanded model of the circuit to verify whether, starting from that current state, the circuit will exhibit the consequent behavior within that finite time under all input signal conditions.

07 Dec 2000
TL;DR: A global modeling concept for modeling microwave circuits is described, which allows the modeling of electromagnetic and thermal effects to be included in the simulation of electronic circuits, by viewing EM and thermal subsystems as subcircuits.
Abstract: CHRISTOFFERSEN, CARLOS ENRIQUE. Global Modeling of Nonlinear Microwave Circuits (Under the direction of Michael B. Steer.) A global modeling concept for modeling microwave circuits is described. This concept allows the modeling of electromagnetic (EM) and thermal effects to be included in the simulation of electronic circuits, by viewing EM and thermal subsystems as subcircuits. Then, circuit analysis techniques are developed from a general state variable reduction formulation. This general formulation, based on the state variables of the nonlinear devices, allows the analysis of large microwave circuits because it reduces the size of the nonlinear system of equations to be solved. One of the derived analysis techniques is based on convolution and therefore provides modeling of frequency-defined network elements not present in conventional circuit simulators. Another analysis technique based on wavelets that would enable the multiresolution analysis of circuits is investigated. Also, a reduced state variable formulation using conventional time marching schemes is developed. It is shown that this can achieve more than an order of magnitude improvement in simulation speed compared to that of traditional circuit simulation methods. All these developments are implemented in a circuit simulator program, called Transim. This program provides unprecedented flexibility for the addition of new device models or circuit analysis algorithms. Transim supports the local reference concept, which is fundamental to the analysis of spatially distributed circuits and also to simultaneous thermal-electrical simulations. Transim is applied to the transient simulation of a 47-section nonlinear transmission line considering frequency dependent attenuation for the first time and the transient simulation, also for the first time, of two quasi-optical power amplifier arrays. Biographical Summary Carlos E. Christoffersen was born in Santa Fe, Argentina in 1968. From 1991 to June 1996 he was a member of the research staff of the Laboratory of Microelectronics of the National University of Rosario, Argentina. He received the Electronic Engineer degree at the National University of Rosario, Argentina in 1993. From 1993 to 1995 he was a research fellow of the National Research Council of Argentina (CONICET). In 1996, he was awarded a Fulbright scholarship to pursue an M.S. degree in the USA. He received the M.S. degree in electrical engineering in 1998 from North Carolina State University. Currently he is pursuing his Ph.D. degree at the same university. Since 1996, he has been with the Department of Electrical and Computer Engineering as a research assistant. He is a member of the IEEE. His research interests include computer aided analysis of circuits and analog, RF and microwave circuit design.

Proceedings ArticleDOI
06 Sep 2000
TL;DR: In this paper, a time-domain shooting method based coupled device and circuit simulator suitable for accurate simulation of RF circuits is presented, which supports accurate numerical models for diodes, BJTs, and MOSFETs.
Abstract: A time-domain shooting method based coupled device and circuit simulator suitable for accurate simulation of RF circuits is presented. The simulator supports accurate numerical models for diodes, BJTs, and MOSFETs. These combined with the accelerated steady-state method allow accurate and efficient steady-state simulation of RF circuits.

Proceedings ArticleDOI
16 Jul 2000
TL;DR: The results of the nonlinear analysis can be used to design and implement better mitigating and control techniques for the circuits under study and provide an alternate representation that can lead to better designs and new ways to explain nonlinear behavior in power electronics circuits.
Abstract: This paper describes the development of software tools for the analysis of chaos in power electronics systems. This project was motivated by potential contributions of chaos theory in the design, analysis and control of power electronics circuits. Nonlinear analysis software and computer programs were used for the detection and analysis of chaotic components. Simulations of power electronics devices were performed using commercially available circuit analysis packages. The voltage and current time series obtained from the circuit analysis were studied using the nonlinear analysis tools developed for this project as well as existing nonlinear analysis programs. The results of the nonlinear analysis can be used to design and implement better mitigating and control techniques for the circuits under study. Chaotic dynamics provide an alternate representation that can lead to better designs and new ways to explain nonlinear behavior in power electronics circuits. There is also a great pedagogical value in complementing the traditional representation of power electronic circuits with alternate models.

Journal ArticleDOI
TL;DR: A behavioral model of a 1.8-V, 6-bit flash analog-to-digital converter has been developed based on device parameters using the g/sub m//I/sub d/ methodology and the performance can be predicted with input only from device and process simulators eliminating the need for a circuit simulator and associated model parameters.
Abstract: A behavioral model of a 1.8-V, 6-bit flash analog-to-digital converter has been developed based on device parameters using the g/sub m//I/sub d/ methodology. This approach eliminates the need for recharacterization of blocks when device sizes are changed. Furthermore, the performance can be predicted with input only from device and process simulators eliminating the need for a circuit simulator and associated model parameters. Signal to noise plus distortion ratio and differential and integral nonlinearity are predicted and verified at lower resolution with a circuit simulator.

Proceedings ArticleDOI
28 May 2000
TL;DR: A method of dealing with numerical problems caused by a singular or nearly singular Jacobian matrix along a zero curve resulting from the use of a continuation method that is not limited to simulators based on homotopy methods only and can be used with any ODE solution algorithm based on a predictor-corrector mechanism.
Abstract: The use of continuation methods has been shown to be more effective than standard Newton-Raphson-based methods in finding the operating point(s) of circuits possessing multiple operating points or in dealing with circuits exhibiting convergence problems in DC. In this paper we propose a method of dealing with numerical problems caused by a singular or nearly singular Jacobian matrix along a zero curve resulting from the use of a continuation method. This method has been implemented in a circuit simulator that uses a continuation method. Using the implementation we were able to achieve a much better convergence rate for some circuits. The proposed method is not limited to simulators based on homotopy methods only; it can be used with any ODE solution algorithm based on a predictor-corrector mechanism. Several circuit examples are given.

Proceedings ArticleDOI
16 Jul 2000
TL;DR: New device models are developed for power diodes and thyristor based devices, such as GTO, IGCT and MTO, based on semiconductor physics, which guarantees a wide range of validity in circuit simulation.
Abstract: Circuit simulation is a powerful tool for the design of high power converters, if suitable device models exist. Unfortunately, the commercially available circuit simulators do not have accurate models for high power semiconductors. Therefore, new device models are developed for power diodes and thyristor based devices, such as GTO, IGCT and MTO. These models are based on semiconductor physics, which guarantees a wide range of validity. Electrical and thermal behavior is implemented, which allows transient temperature simulation. The models are programmed in the C++ language and are implemented in the widely used circuit simulator PSpice using the Device Equation Options. Simulation results are compared with measurements.

Proceedings ArticleDOI
08 Aug 2000
TL;DR: In this article, the nonlinear behavior of common-emitter (CE) and single-balanced BJT mixer (SBM) circuits is described by a simple closed-form interpretable analytical expression, which is in good agreement with harmonic-balance results of an APLAC circuit simulator for different input signal level, biasing current, emitter degeneration and operating frequency range.
Abstract: The nonlinear behavior of common-emitter (CE) and single-balanced BJT mixer (SBM) circuits is described by a simple closed-form interpretable analytical expression. The third-order intermodulation distortion (IM3) calculated by this approach is in good agreement with harmonic-balance results of an APLAC circuit simulator for different input signal level, biasing current, emitter degeneration and operating frequency range. In addition, the model can successfully identify the bias currents that lead to a minimum or maximum amount of distortion. Therefore, it provides an easy guideline for the designer to directly optimize the linearity performance among other conflicting performance parameters; gain, noise and power dissipation.