Showing papers on "Electronic circuit simulation published in 2003"

Circuit simulator models for the diode and IGBT with full temperature dependent features

Abstract: The problems faced in generating analytical models for the insulated gate bipolar transistor (IGBT) and power diode are devising correct equations and determining realistic boundary conditions, especially for two-dimensional (2-D) features, while ensuring convergence of the models. These issues are addressed in this paper in relation to the temperature dependent modeling of NPT IGBTs and diodes. Simulation and experimental results are presented and compared to validate the modeling approach.

System and method for simulating a circuit having hierarchical structure

Abstract: A system for simulating a circuit having hierarchical data structure includes a simulator module having one or more computer programs for 1) creating a static database in accordance with a netlist description of the circuit, where the static database contains topology information of the circuit; 2) selecting a group circuit for simulation, where the group circuit contains one or more leaf circuits selected from the first branch and the second branch; 3) creating a dynamic database for representing the group circuit, where the dynamic database includes references to the static database for fetching topology information dynamically during simulation; and 4) simulating the group circuit in accordance with the dynamic database. Since the system duplicates and reproduces only the relevant dynamic information when necessary, the disclosed circuit simulator uses less memory and produces better performance.

Design and Performance of High Tc Superconducting Coplanar Waveguide Matching Circuit for RF-CMOS LNA

Abstract: SUMMARY As an RF high Tc superconducting (HTS) front end for a microwave receiver, we propose a new design method for the broadband matching circuit composed of coplanar waveguide (CPW) meanderline resonators connecting a slot antenna with CMOS low noise amplifier (LNA). The parameters of the antenna sections with matching circuit are calculated and simulated with the circuit simulator and electromagnetic field simulator. CMOS LNA was designed and its input and output impedances and noise figure were obtained by SPICE simulation.

Circuit simulation method

Abstract: In an inventive circuit simulation method, simulation is performed utilizing a circuit simulator, based on a netlist prepared using mask layout data for a circuit, and parameters obtained from measurement data concerning the characteristic of each transistor. The parameters are extracted from the measurement data based on not only the transistor size but also a stress applied to the transistor. Therefore, the circuit simulation can be performed with precision and accuracy never before possible, in consideration of a change in the characteristic of the transistor which is caused by the stress applied thereto.

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits

Abstract: This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. Particularly, the extension of the recent MIB model for single/multi gate symmetric/asymmetric device for a wide range of drain to source voltage and temperature is addressed. Circuit level co-simulations are successfully performed by implementing the SET analytical model in Analog Hardware Description Language (AHDL) of a professional circuit simulator SMARTSPICE. Validation at device and circuit level is carried out by Monte-Carlo simulations. Some novel functionality hybrid CMOS-SET circuit characteristics: (i) SET neuron, (ii) Multiple valued logic circuit and (iii) a new Negative Differential Resistance (NDR) circuit, are also predicted by the proposed SET model and analyzed using the new hybrid simulator.

A new empirical nonlinear model for sub-250 nm channel MOSFET

Abstract: An empirical nonlinear model for sub-250 nm channel length MOSFET is presented which is useful for large signal RF circuit simulation. Our model is made of both analytical drain current and gate charge formulations. The drain current expression is continuous and infinitely derivable, and charge conservation is taken into account, as the capacitances derive from a single charge expression. The model's parameters are first extracted, prior the model's implementation into a circuit simulator. It is validated through dc, ac, and RF large signal measurements compared to the simulation.

Circuit simulation bus transaction analysis

Abstract: While simulating a circuit described by the netlist, a circuit simulator produces a dump file containing a set of waveform data sequences, each corresponding to a separate signal within the circuit, and representing states of its corresponding signal at a succession of times during the circuit simulation. Based on a mapping of the waveform data sequences to lines of a bus, and on transaction data models describing characteristic signal patterns appearing on the bus during each type of transaction that can occur on the bus, a transaction analysis system identifies transactions that occurred on the bus during the simulation. The transaction analysis system also notes a time during the circuit simulation in which each transaction occurred, and generates a display including a separate representation of each identified transaction positioned to represent the time the transaction occurred.

System and method for guiding and optimizing formal verification for a circuit design

Abstract: The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.

Use of SABER circuit simulation software for the modeling of compensated pulsed alternators driving a railgun load

Abstract: A railgun launcher requires very high current pulsed power over the period of a few milliseconds. For laboratory systems, capacitor banks have traditionally been used to provide this energy, but field applications require a system with significantly higher energy storage density. Rotating machines that store the energy in the form of rotational kinetic energy and can quickly convert that energy to high current electrical energy have been designed and built. These low-impedance, multiphase, multipole synchronous generators are referred to as pulsed alternators. The AC output of the pulsed alternator is rectified to provide DC to power the railgun. The design of the rectifier set and control circuitry is very dependent on the alternator characteristics; to facilitate the design and evaluation of the overall pulsed power system, a modeling tool which accurately represents the performance of the pulsed alternator while allowing easy changes to the external circuitry and controls is needed. This paper describes a manner in which these pulsed alternators can be accurately modeled. The simulation platform SABER was chosen because of the robust modeling engine, the ease of integrating mechanical components, and the large library of existing models for a wide range of electrical components.

Dielectric losses of capacitor and ferrite core in an LCT component

Abstract: The lumped component equivalent circuit of an inductor capacitor transformer integrated component (LCT) is deduced from a set of impedance measurements. This circuit allows the whole electronic behavior of the component, including losses, to be accurately forecast by using standard electronic simulation software. A closer look at experimental data reveals that several physical phenomena, often neglected, have a strong impact on LCT electrical properties. Dielectric losses in the capacitor and permittivity related losses in ferrite core are among them. To sum up, this paper lists main phenomena to account for in future field computations, it supplies a suitable equivalent circuit that accounts for them and it shows how to extract all its element values from a set of impedances deductible from field computations.

Predicting short circuit power from timing models

Abstract: Power dissipation is becoming a major show stopper for integrated circuit design especially in the server and pervasive computing technologies. Careful consideration of power requirements is expected to bring major changes in the way we design and analyze integrated circuit performance. This paper proposes a practical methodology to evaluate the short-circuit power of static CMOS gates via effective use of timing information from timing analysis. We introduce three methods to estimate short-circuit power of a static CMOS circuit without requiring explicit circuit simulation. Our proposed methodology offers practical advantages over previous approaches, which heavily rely on simple special device models. Proposed approach is experimented with an extensive set of benchmark examples and several device models and found very accurate.

A new physics based SPICE model for NPT IGBTs

Abstract: A physics based, non-punch-through, insulated gate bipolar transistor (NPT-IGBT) model is presented, as well as its porting into available circuit simulator SPICE. Developed model results in a system of ODEs, from which time/space hole/electron distribution is obtained, and is based on solution of ambipolar diffusion equation (ADE) through a variational formulation, with one-dimensional simplex finite elements. Model implementation, in a circuit simulator, is made by means of an electrical analogy with the resulting system of ODEs. Other parts of the devices are modeled using standard methods. Thus, this new hybrid model combines advantages of numerical and mathematical methods, through modeling charge carrier behavior with high accuracy even maintaining low execution times.

Two-dimensional SPICE-linked multiresolution impedance method for low-frequency electromagnetic interactions

Abstract: A multiresolution impedance method for the solution of low-frequency electromagnetic interaction problems typically encountered in bioelectromagnetics is presented. While the impedance method in its original form is based on the discretization of the scattering objects into equal-sized cells, our formulation decreases the number of unknowns by using an automatic mesh generation method that does not yield equal-sized cells in the modeling space. Results indicate that our multiresolution mesh generation scheme can provide a 50%-80% reduction in cell count, providing new opportunities for the solution of low-frequency bioelectromagnetic problems that require a high level of detail only in specific regions of the modeling space. Furthermore, linking the mesh generator to a circuit simulator such as SPICE permits the addition of arbitrarily complex passive and active circuit elements to the generated impedance network, opening the door to significant advances in the modeling of bioelectromagnetic phenomena.

System-level modeling and Simulation of the 10G optoelectronic interconnect

Abstract: Mixed-signal multidomain systems present a challenge for computer-aided design tools Optical and electronic simulation tools are available as separate entities However, to date, successful system-level cosimulation has not been implemented, leading to expensive refabrication We present a unique system-level simulation tool for mixed electrooptical systems We apply our tool Chatoyant to the simulation of an optical high-speed free-space interconnect system designed for 10-GHz speeds The 10G free-space optical interconnect module has optical, optoelectronic, and microwave components and thus is an ideal vehicle to use as a test system We demonstrate how Chatoyant, a mixed-signal multidomain simulator, has been used to evaluate end-to-end performance of this complex system, including the exploration of design tradeoffs and mechanical tolerancing

An overview of algorithms in Gnucap

Abstract: This paper will present an overview of the algorithms in Gnucap. Gnucap is a mixed-signal circuit simulator. Algorithms to be presented include event driven analog simulation, the use of queues to accelerate simulation of large circuits, implicit mixed-mode simulation, where the simulator automates the interface between analog and digital portions of the circuit. These algorithms provide equivalent accuracy to Spice with significant speedup for some classes of circuits, including large mostly passive circuits with a few active devices, and large mixed-mode circuits with latency. An overview of work in progress will also be given. This includes cached model evaluation, which will exploit hierarchy and duplication in the circuit, and true multi-rate simulation.

Non-linear modelling of microwave PIN diode switches for harmonic and intermodulation distortion simulation

Abstract: The paper presents for the first time a practical and relatively simple non-linear modeling solution for /spl mu/-wave PIN diodes for use in harmonic balance (HB) circuit simulators. It enables very good prediction performance of the very important harmonic and intermodulation characteristics of these devices when used in typical /spl mu/-wave switching applications. Accurate harmonic distortion measurements have been performed on a number of commercial surface mount PIN diodes, over a wide range of relevant bias conditions and RF power levels. Parasitic elements are first extracted from microwave S-parameter data. Separate non-linear circuit models are then used for the ON and OFF states of the PIN diodes, and these are directly optimized on the measured harmonic distortion data using a dedicated modeling platform developed within a commercial modeling software tool. The new models have been implemented and tested in a popular harmonic balance circuit simulator with very good results. The modeling solution described here can be also applied to other active devices for similar large-signal modeling problems.

Analysis modeling and simulation of low-voltage MOSFETs in synchronous-rectifier buck-converter applications

Abstract: Nowadays voltage regulator modules (VRMs) are high switching frequency applications devoted to supply low-voltage and high current with more and more increasing slew rates. Excellent performances can be provided by using a synchronous-rectifier buck converter, which allows overcoming the limitations in terms of efficiency shown by a standard buck topology with Schottky diode. A proper design of the synchronous-rectifier is fundamental to obtain the desired performance from the converter due to its considerable contribute to the total power losses. In this paper analysis modeling and simulation of low-voltage power MOSFETs in synchronous-rectifier buck-converter applications are reported. The MOSFET model has been derived by using an advanced process simulator, which represents the device as a two-dimensional (2-D) finite-element grid. Structure parameters have been derived from flow-chart data pertaining to the MOSFET fabrication, which have been optimised by comparing measured and simulated electrical characteristics. Static and dynamic behaviors relative to the studied device have been simulated through a 2-D mixed device and circuit simulator, and used to extract the structure parameters till to obtain a good match with the experimental results. A synchronous-rectifier buck-converter application has been experimentally analysed by arranging a suitable breadboard, in which the same device type has been used for both the high-side and low-side switch. Simulation runs, performed by implementing a behavioral model of the MOSFET device, have been reported too.

A New Physics Based SPICE Sub-circuit Model for Insulated Gate Bipolar Transistors (IGBTs)

Abstract: A physics based, Non-Punch-Through, Insulated Gate Bipolar Transistor (NPT-IGBT) model is presented, as well as its porting into available circuit simulator SPICE. The developed model results in a system of ODEs, from which time/space hole/electron distribution is obtained, and is based on solution of ambipolar diffusion equation (ADE) trough a variational formulation, with posterior implementation using one-dimensional simplex finite elements. Other parts of the device are modeled using standard methods. Thus, this new hybrid model combines either advantages of numerical methods or mathematical, through modeling charge carrier behavior with high accuracy even maintaining low execution times. Implementation of the model in a general circuit simulator is made by means of an electrical analogy with the resulting system of ODEs.

Statistical delay simulation device for lsi and its simulation method

Abstract: PROBLEM TO BE SOLVED: To estimate dispersion of a delay in an LSI in a design step for easily and surely reflecting the estimation result to delay simulation of the LSI. SOLUTION: A statistical delay simulation device 10 is provided with a circuit simulator 11 simulating circuit operation of a circuit cell constituting the LSI, a statistical delay library creation device 12 creating a statistical delay library 104 describing dependency of delay dispersion in each circuit on a predetermined operation condition according to a process parameter 101 and the like, a delay calculator 13 calculating a delay quantity of each circuit cell and creating a statistical LSI delay information file 107 including the delay data, and a static timing analyzer 15 simulating operations including the delay dispersion of the LSI on the basis of the data of the statistical LSI delay information file 107 and creating a statistical LSI delay analysis result file 108. COPYRIGHT: (C)2004,JPO&NCIPI

Method and apparatus for providing an interface to an electronic design of an integrated circuit

Abstract: Method, apparatus, and computer readable medium for producing an interface description for an electronic design of an integrated circuit is described. By example, the electronic design includes a plurality of circuit descriptions representing the behavior of circuit elements. One or more circuit descriptions from the electronic design are selected to produce interface description. The one or more selected circuit descriptions include a subset of the plurality of circuit descriptions of the electronic design. A processor for modifying the electronic design is obtained. The electronic design is then processed using the processor with the interface description as parametric input.

Physically based models of high power semiconductors including transient thermal behavior

Abstract: Circuit simulation is a powerful tool for the design of high power converters, if suitable device models exist. Unfortunately, the commercially available circuit simulators do not have accurate models for high power semiconductors. Therefore, new device models are developed for power diodes and thyristor based devices, such as GTO, IGCT, and MTO. These models are based on semiconductor physics, which guarantees a wide range of validity. Electrical and thermal behavior is implemented, which allows transient temperature simulation. The models are programmed in the C++ language and are implemented in the widely used circuit simulator PSpice using the device equation option. Simulation results are compared with measurements.

A Charge Balanced C-V Converter for a Differential Capacitance Sensor

Abstract: This paper presents a simple new configuration for a switched capacitor type C-V converter based on a charge balance principle for a differential capacitance sensor and its simulation results. The new converter was devised and realized using only one operational amplifier, nine CMOS switches and an oscillation circuit. It was shown that the offset output due to the input offset voltage of an operational amplifier can be ideally reduced to zero with an appropriate additional switch configuration. By using a P-Spice circuit simulator, the offset cancellation scheme and proper transient response were confirmed for possible parasitic capacitances concerned in a typical differential capacitance sensor. In addition, a P-Spice system simulation based on analog behavioral models enabled us to reliably estimate the operation of an electro-mechanical system with the C-V converter statically and dynamically, where the electrostatic force acting on a movable electrode was taken into account.

SPICE-based simulation website: application to teaching of power electronics

Abstract: High prices and hardware requirements considerably limit the access to CAD tools by educational institutions or students, and free versions of commercial software are not education-oriented and usually lack well-implemented numerical algorithms and device models. In order to overcome these limitations, a website has been designed and made available to Internet users, allowing them to perform simulations of electronic circuits. An additional module has been built in the package that permits students to examine intrinsic phenomena occurring in a power device.

MATLAB - SPICE interface (MATSPICE) and its applications

Abstract: This paper introduces an interface between MATLAB and SPICE, some of its applications will be introduced and examples on these applications will be illustrated. This interface allows the circuit designer to use all the benefits of the circuit level simulators under the MATLAB environment. This avoids many manual steps done on the simulator. Simulation results are transferred to MATLAB to be analyzed using the powerful MATLAB toolboxes. The scope of the applications of MATSPICE is huge and depends on the circuit designer. The applications in this paper will be in the circuit sizing and in the automatic verification of MATLAB circuit and device models. MATSPICE can be a part of a more general synthesis tool as will be shown in the examples.

A new efficient equivalent circuit extraction method for multi-port high speed package using multi-input multi-output transmission matrix and polynomial curve fitting

Abstract: Modem high-speed integrated circuits for multi-gigabit applications require high-density packages with several hundred YO pins, which also require a wideband circuit model of package. Since a wideband model of a multi-port network is generally calculated by a full-wave field solver and given in the form of a scattering parameter, a SPICEcompatible circuit model must be extracted from a scattering matrix. We present the concrete maxtrix formulation for tranforming scattering parameter to transmission matrix for a ZN-port network . This transformation results in a new efficient equivalent circuit extraction method, which conveniently incorporates accurate electromagnetic models of an interconnecting structure including electronic package into a circuit simulator. By using this new exfraction method, we can easily determine the valid bandwidth of an equivalent circuit model .

Method for simulating semiconductor device, method for calculating deterioration degree, method for calculating deterioration parameter and method for designing semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a design technology of a semiconductor device capable of eliminating necessity for a voltage file by calculating a hot carrier deterioration in parallel with a circuit simulation and improving the simulation speed. SOLUTION: A method for simulating the semiconductor device comprises a library 1 of circuit net lists, a combination simulator 2 for combining a circuit simulation and a transistor operation change simulation by using various types of information of the library 1, and a circuit operation file 3 for storing information of a circuit operation of a delay due to deterioration or the like, in an integrating system for calculating an overall performance change in such a manner that circuit and transistor operation change simulation engines 4, 5 are provided in the simulator 2, and the circuit simulator and a simulator for calculating the change of the transistor operation are combined to one program. COPYRIGHT: (C)2003,JPO

The missing kink to seamless simulation [nanometer CMOS ULSI]

Abstract: This paper reviews the trends and needs in multilevel modeling in the context of nanometer CMOS ULSI systems, with an emphasis from the model/tool developer's perspective. A dual representation of the transistors/circuit is proposed and demonstrated through physics-based compact modeling and a single-engine circuit simulator based on subcircuit expansion. Extension to process correlation and block-level representation is also proposed, which will be the key to studying process effects on system performance. This consistent dual representation allows detailed physics captured at a lower level to be propagated to the higher level of abstraction. The key idea is to build a physics-based device compact model (CM) based on technology characterization, which serves as the building block for an implicit multilevel circuit simulator based on a subcircuit-expansion approach. In this way, process variation can be captured through device CMs, and its effects on circuit/system performance can be linked to a consistent hierarchy of abstractions within the same simulator engine.

Non-linear electro thermal model of LDMOS power transistor coupled to 3D thermal model in a circuit simulator

Abstract: In this article, we introduce a new approach for electro thermal modelling of power LDMOS transistor. The electrical description of each intrinsic component is done with 3D bi-cubic splines. The electrical model is coupled to a 3D thermal model stemming from FEA simulation. This full 3D electro thermal model is used with the ADS circuit simulator.