Showing papers on "Electronic circuit simulation published in 2004"

Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design

Abstract: A physically based compact analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the "orthodox theory" of single electron tunneling, and valid for single or multi gate, symmetric or asymmetric devices and can also explain the background charge effect. The model parameters are physical device parameters and an associated parameter extraction procedure is reported. The device characteristics produced by the proposed model are verified with Monte Carlo simulation for large range of drain to source voltages (|V/sub DS/|/spl les/3e/C/sub /spl Sigma//) and temperatures [T/spl les/e/sup 2//(10k/sub B/C/sub /spl Sigma//)] and good agreements are observed. The proposed model is implemented in a commercial circuit simulator in order to develop a computer-aided design framework for CMOS-SET hybrid IC designs. A series of SPICE simulations are successfully carried out for different CMOS-SET hybrid circuits in order to reproduce their experimental/Monte Carlo simulated characteristics.

A coupled efficient and systematic full-wave time-domain macromodeling and circuit Simulation method for signal integrity analysis of high-speed interconnects

Abstract: This paper presents an accurate and systematic approach for analysis of the signal integrity of the high-speed interconnects, which couples the full-wave finite difference time domain (FDTD) method with scattering (S) parameter based macromodeling by using rational function approximation and the circuit simulator. Firstly, the full-wave FDTD method is applied to characterize the interconnect subsystems, which is dedicated to extract the S parameters of the subnetwork consisting of interconnects with fairly complex geometry. Once the frequency-domain discrete data of the S parameters of the interconnect subnetwork is constructed, the rational function approximation is carried out to establish the macromodel of the interconnect subnetwork by employing the vector fitting method, which provides a more robust and accurate solution for the overall problem. Finally, the analysis of the signal integrity of the hybrid circuit can be fulfilled by using the S parameters based macromodel synthesis and simulation program with integrated circuits emphasis (SPICE) circuit simulator. Numerical experiments demonstrate that the proposed approach is accurate and efficient to address the hybrid electromagnetic (interconnect part) and circuit problems, in which the electromagnetic field effects are fully considered and the strength of SPICE circuit simulator is also exploited.

Reduced-order modeling of weakly nonlinear MEMS devices with Taylor-series expansion and Arnoldi approach

Abstract: In this paper, we present a new technique by combining the Taylor series expansion with the Arnoldi method to automatically develop reduced-order models for coupled energy domain nonlinear microelectromechanical devices. An electrostatically actuated fixed-fixed beam structure with squeeze-film damping effect is examined to illustrate the model-order reduction method. Simulation results show that the reduced-order nonlinear models can accurately capture the device dynamic behavior over a much larger range of device deformation than the conventional linearized model. Compared with the fully meshed finite-difference method, the model reduction method provides accurate models using orders of magnitude less computation. The reduced MEMS device models are represented by a small number of differential and algebraic equations and thus can be conveniently inserted into a circuit simulator for fast and efficient system-level simulation.

A fast hybrid field-circuit simulator for transient analysis of microwave circuits

Abstract: A plane-wave-time-domain accelerated time-domain integral-equation solver is coupled to a SPICE-like transient circuit simulator to analyze electromagnetic platform-circuit interactions. The hybrid field-circuit simulator simultaneously solves surface-wire-volume time-domain integral equations that model electromagnetic interactions with the platform and modified nodal analysis equations that govern the behavior of the potentially nonlinear lumped circuits. A shielded nonlinear microwave amplifier is analyzed using the proposed scheme, and its immunity to electromagnetic interference is assessed.

Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method

Abstract: An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general layout and wiring information related to devices and wirings included in the electronic circuit, user requirements defined by a user, and user resources defined by the user, and urging an input to the user by displaying the design constraints.

Analysis of split-drain MAGFETs

Abstract: We present fully three-dimensional simulation results of two-drain and three-drain magnetic field-effect transistors (MAGFET), magnetic sensors based on metal-oxide-semiconductor field-effect transistor (MOSFET) structures. By proper development and discretization of the current density equations comprising the nonzero magnetic field components, a two-drain MAGFET is analyzed at both 77 K and 300 K. The discretization scheme is implemented in the general purpose multidimensional device and circuit simulator MINIMOS-NT which is used to investigate the relative sensitivity, the main figure of merit of any magnetic sensor, as a function of the geometric parameters and bias conditions. Besides, the physical modeling of silicon at 77 K and the Hall scattering factors for the silicon inversion layers are discussed. Our simulation results perfectly match the available experimental data. New in-depth knowledge can be obtained by simulating MOSFET structures at 77 K in the presence of an arbitrary magnetic field.

Circuit statistical modeling for partially correlated model parameters

Abstract: A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.

Extraction of heat-transfer macromodels for MEMS devices

Abstract: In this paper, a model order reduction technique for MEMS heat-transfer system-level modeling is presented. A 3D heat-transfer solver, which is appropriate for MEMS thermal analysis, is implemented using the finite-difference method (FDM). The numerical models generated by the FDM solver can be reduced into low-order macromodels by an Arnoldi-based technique. This order reduction operation has been implemented as an automatic process. Because the macromodels are generated from the finite-element or the finite-difference (FEM/FDM) approximation of the original solid models, they preserve the original characteristics for most operation conditions. Also, since the orders of the macromodels are much less than those of their original FEM/FDM models, the computational costs are significantly reduced by about two to four orders of magnitude. This performance improvement thus makes the macromodels compatible for system-level or circuit simulations, which is essential for overall performance prediction. We also demonstrate that the macromodel results are in good agreement with the experimental results. The macromodels are also converted into the circuit component modules written by the hardware description language, and are inserted into a circuit simulator for system-level simulations with other circuit components.

MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation

Abstract: In this paper, we present a compact model for silicon-on-insulator (SOI) laterally double diffused (LD) MOSFETs. The model is complete insofar as it uses no subcircuits, and is intended to predict device operation in all regions of bias. The device current is described by two main equations handling the MOS channel and the drift region, both of which are smooth and continuous in all operating regimes. Attention is also given to the modeling of inversion at the back oxide to ensure correct behavior is predicted for a source follower in power control applications ("high side operation"). A surface-potential-based formulation is used for the inversion/accumulation channel giving smooth transitions between different regions of operation, and care has been taken to ensure all expressions are smooth and infinitely differentiable to achieve the best possible convergence performance. Self (and coupled) heating effects exert a major influence over the behavior of power SOI devices, and these issues are incorporated in the model core in a consistent fashion. The model has been installed in a commercial SPICE-type circuit simulator and evaluated against individual devices and complete circuits fabricated in an industrial smart power SOI process. Accuracy is significantly improved with respect to the existing LDMOS models, and convergence behavior in switching and linear circuit simulations is comparable with industry standard models of this complexity.

Apparatus for statistical LSI delay simulation

Abstract: A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.

A new approach for closed-form transient analysis of multiconductor transmission lines

Abstract: A novel closed-form model for multiconductor transmission lines is presented. The proposed model is derived from the analytical characterization of half-T ladder networks, which using closed-form polynomials (named DFF and DFFz), allow one to exactly extract poles and residues of the two-port representation of multiconductor transmission lines, thus, generating a time domain macromodel that can be incorporated in a circuit simulator. Since the model is derived from a stable and passive equivalent network, its stability and passivity are strictly preserved. Simulation results for one, two, and three-conductor transmission lines with linear and nonlinear terminations are presented, confirming the validity of the proposed model.

Apparatus and method for statistical LSI delay simulation

Abstract: A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.

Non-quasi-static model for MOSFET based on carrier-transit delay

Abstract: A non-quasi-static MOSFET model for circuit simulation, which is based on the carrier-transit delay responsible for the channel formation during switching on, has been developed. The developed model was implemented into a circuit simulator, and good agreement of transient drain current with 2D simulation results was confirmed.

Electromagnetic and thermal coupled analysis of ferrite orthogonal-core based on three-dimensional reluctance and thermal-resistance network model

Abstract: In this paper, we propose an electromagnetic and thermal coupled analysis of a ferrite orthogonal-core variable inductor based on the equivalent circuit theory. A three-dimensional reluctance network model and thermal-resistance network model are combined with each other, and calculated simultaneously on a general purpose circuit simulator SPICE.

Noise Wave Modeling of Microwave Transistors Based on Neural Networks

Abstract: The noise modeling of microwave FETs based on the noise-wave representation of a transistor-intrinsic circuit is considered. Frequency-dependent noise-wave temperatures are introduced as empirical model parameters and modeled using neural networks. In this way, online optimization in a circuit simulator is shifted to offline training of neural networks. An example of transistor-noise modeling for one specified component is shown. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 41: 294–297, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20120

On the impulse circuit model for the single-electron tunnelling junction

Abstract: SUMMARY In this paper, the impulse circuit model for the single-electron tunnelling (SET) junction is discussed Starting from well-known results of the so-called orthodox theory of single electronics, an equivalent circuit for the single-electron tunnelling junction is ‘derived’ by examining the behaviour of simple circuits including a SET junction In the impulse circuit model, the electron tunnelling event is basically implemented by an impulsive current source with value e� (t − t0), which absorbs exactly the energy delivered by the sources that is not stored in the circuit The equivalent circuit consisting of a charged capacitor in parallel with the impulsive current source does not contain a tunnel resistance, and the critical voltage is expressed in only local parameters The impulse model is suitable for implementation in a circuit simulator; results of a SPICE simulation of the single-electron pump are shown Copyright ? 2004 John Wiley & Sons, Ltd

Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing

Abstract: Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel technique for the efficient simulation-based exploration of high-dimensional performance spaces is presented. To this end, fundamental circuit design knowledge is described by constraint functions. Based on a linearization of the latter and of the circuit performance functions, a description of the feasible performance range in the form of a polytope is derived. Moreover, the approach is integrated into a hierarchical sizing method, where it propagates topological and technological constraints bottom-up. Practical application results demonstrate the efficiency and usefulness of the new method.

Artificial neural network modeling of RF MEMS resonators

Abstract: In this article, a novel and efficient approach for modeling radio-frequency microelectromechanical system (RF MEMS) resonators by using artificial neural network (ANN) modeling is presented. In the proposed methodology, the relationship between physical-input parameters and corresponding electrical-output parameters is obtained by combined circuit/full-wave/ANN modeling. More specifically, in order to predict the electrical responses from a resonator, an analytical representation of the electrical equivalent-network model (EENM) is developed from the well-known electromechanical analogs. Then, the reduced-order, nonlinear, dynamic macromodels from 3D finite-element method (FEM) simulations are generated to provide training, validating, and testing datasets for the ANN model. The developed ANN model provides an accurate prediction of an electrical response for various sets of driving parameters and it is suitable for integration with an RF/microwave circuit simulator. Although the proposed approach is demonstrated on a clamped-clamped (C-C) beam resonator, it can be readily adapted for the analysis of other micromechanical resonators. © 2004 Wiley Periodicals, Inc. Int J RF and Microwave CAE 14: 302–316, 2004.

Multilevel device models developed for the virtual test bed (VTB)

Abstract: Model levels for power semiconductor devices are described in the context of the virtual test bed simulation environment. The five model levels proposed are universal in nature and can be adopted for categorization of device models in any circuit simulator or finite element (or finite difference) simulator. These levels begin with simple behavioral models, then move to physics-based models of various complexity. This work concentrates on the development and discussion of the model levels-1, -2, and -3. As an example, the case of an integrated gate-commutated thyristors (IGCT) is discussed in detail, and simulation and experimental results are provided and compared.

Causal reduced-order modeling of distributed structures in a transient circuit Simulator

Abstract: Fosters' canonical representation of the transfer characteristic of a linear system is the key to causal fully convergent incorporation of distributed structures in transient circuit simulators. The implementation of the Foster's model in the fREEDA circuit simulator is reported and the modeling of a two-port coupled inductor is presented as an example.

Modeling of integrated monolithic transformers for silicon RF IC

Abstract: We present a compact and scalable model for on-chip transformers fabricated in silicon IC technology The model is driven from the layout and the process technology specifications It is suitable for design optimization and circuit simulation EM-simulation is used to validate the model The proposed model shows excellent agreement with EM-simulation over a large frequency range (1-15 GHz)

Circuit simulation system with simulation models assigned based on layout information and connection information

Abstract: A circuit simulation system for simulating an integrated circuit includes a circuit behavior analysis module analyzing behavior information of a circuit element of the integrated circuit based on connection information; a model selection module selecting a circuit element model corresponding to the circuit element from the library area based on location information and behavior information of the circuit element; a circuit generation module generating a to-be-analyzed circuit using the selected circuit element model; and a circuit simulation module executing the to-be-analyzed circuit simulation.

HiSIM: hierarchical interconnect-centric circuit simulator

Abstract: To ensure the power and signal integrity of modern VLSI circuits, it is crucial to analyze huge amount of nonlinear devices together with enormous interconnect and even substrate parasitics to achieve the required accuracy. Neither traditional circuit simulation engines such as SPICE nor switch-level timing analysis algorithms are equipped to handle such a tremendous challenge in both efficiency and accuracy. We establish a solid framework that simultaneously takes advantage of a hierarchical nonlinear circuit simulation algorithm and an advanced large-scale linear circuit simulation method using a new predictor-corrector algorithm. Under solid convergence and stability guarantees, our simulator, HiSIM, a hierarchical interconnect-centric circuit simulator, is capable of handling the post-layout RLKC power and signal integrity analysis task efficiently and accurately. Experimental results demonstrate over 180X speed up over the conventional flat simulation method with SPICE-level accuracy.

Employing a ground model to accurately characterize electronic devices measured with GSG probes

Abstract: Traditionally, when measuring an electronic device, the nonideal (non-50 /spl Omega/) electrical behavior of the ground-signal-ground probes is removed through calibration. However, this procedure does not allow for an accurate measurement of devices that exhibit an unbalanced flow of electrical currents through the two ground fingers of the probe. We found that a simple interface circuit can be used by a circuit simulator, such as ADS, to reproduce the measurements of devices in which unbalanced ground currents flow in the return paths. A simple experimental method to determine the interface circuit is given.

Model stamping matrix check technique in circuit simulator

Abstract: The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining whether entries in model stamping matrices interrelate according to a plurality of preset rules before circuit equations are solved.

Efficient thermal modeling of SOI MOSFETs for fast dynamic operation

Abstract: An efficient dynamic thermal model has been developed for silicon-on-insulator (SOI) MOSFETs. The model is derived from the variational principle using a thermal functional, and is able to describe extremely fast dynamic thermal behavior in SOI devices subjected to sudden changes in power generation. The developed model is further converted into a thermal circuit with time-varying thermal resistances and capacitances. With the circuit implemented in a circuit simulator, these time-varying thermal resistances and capacitances are able to reasonably capture extremely fast temperature evolution in SOI devices without including a large number of nodes. The developed dynamic thermal model and circuit are verified with the rigorous device simulation including self-heating.

Destruction-free parameter extraction for a physics-based circuit simulator IGCT model

Abstract: This paper presents a practical destruction-free parameter-extraction methodology for a new physics-based circuit simulator buffer-layer integrated gate-commutated thyristor (IGCT) model. Most key parameters needed for this model can be extracted by one simple clamped inductive-load switching experiment. To validate this extraction method, a clamped inductive-load switching experiment was performed, and corresponding simulations were carried out by employing the IGCT model with parameters extracted through the presented methodology. Good agreement has been obtained between the experimental data and simulation results

The influence of geometry and temperature on the parameters of integrated capacitors

Abstract: The research in this paper is focused on poly-poly capacitors, whose electrodes are built of polysilicon with insulation layer (SiO2) between them. Different models are used for characterization - cpolybr3, cpoly and cpolyrf. Some of them present the capacitor as a three terminal device (cpolybr3, cpolyrf). The simulations are done in the CADANCE environment with Spectre Circuit Simulator. Different connections are made to explore the influence of the layout over the basic characteristics of the capacitor, depending on the number of stripes (parts the capacitor is split into). The value of the explored integrated capacitors is 0.1÷5pF. Two technologies are used – AMS 0.35 um SiGe BiCMOS and 0.8 um SiGe BiCMOS.

Non-linear electro thermal model of LDMOS power transistor coupled to 3D thermal model in a circuit simulator

Abstract: In this article, we introdnee a new approach for Electro Thermal modeling of power LDMOS transistor. The electrical description of each intrinsic component is done with 3D Bi-Cubic Splines. The electrical model is coupled to a 3D thermal model stemming from FEA simulation. This full 3D Electro Thermal model is used with the ADS circuit simulator.

Verification method and system for logic circuit

Abstract: A shared register row is provided between a program-based circuit simulator and a device-based circuit simulator. The shared register row includes a plurality of shared registers each corresponding to signals transmitted between the program-based and device-based circuit simulators. By mutually accessing a shared register corresponding to a signal from the program-based and device-based circuit simulators, the signal is transferred via the corresponding shared register with synchronization between the program-based and device-based circuit simulators.