Showing papers on "Electronic circuit simulation published in 2008"

Analog Integrated Circuits for Communication: Principles, Simulation and Design

Abstract: Analog Integrated Circuits for Communication: Principles, Simulation and Design, Second Edition covers the analysis and design of nonlinear analog integrated circuits that form the basis of present-day communication systems. Both bipolar and MOS transistor circuits are analyzed and several numerical examples are used to illustrate the analysis and design techniques developed in this book. Especially unique to this work is the tight coupling between the first-order circuit analysis and circuit simulation results. Extensive use has been made of the public domain circuit simulator Spice, to verify the results of first-order analyses, and for detailed simulations with complex device models. Highlights of the new edition include: A new introductory chapter that provides a brief review of communication systems, transistor models, and distortion generation and simulation. Addition of new material on MOSFET mixers, compression and intercept points, matching networks. Revisions of text and explanations where necessary to reflect the new organization of the book Spice input files for all the circuit examples that are available to the reader from a website. Problem sets at the end of each chapter to reinforce and apply the subject matter. An instructors solutions manual is available on the book's webpage at springer.com. Analog Integrated Circuits for Communication: Principles, Simulation and Design, Second Edition is for readers who have completed an introductory course in analog circuits and are familiar with basic analysis techniques as well as with the operating principles of semiconductor devices. This book also serves as a useful reference for practicing engineers.

Stochastic formulation of SPICE-type electronic circuit simulation with polynomial chaos

Abstract: A methodology for efficient tolerance analysis of electronic circuits based on nonsampling stochastic simulation of transients is formulated, implemented, and validated We model the stochastic behavior of all quantities that are subject to tolerance spectrally with polynomial chaos A library of stochastic models of linear and nonlinear circuit elements is created In analogy to the deterministic implementation of the SPICE electronic circuit simulator, the overall stochastic circuit model is obtained using nodal analysis In the proposed case studies, we analyze the influence of device tolerance on the response of a lowpass filter, the impact of temperature variability on the output of an amplifier, and the effect of changes of the load of a diode bridge on the probability density function of the output voltage The case studies demonstrate that the novel methodology is computationally faster than the Monte Carlo method and more accurate and flexible than the root-sum-square method This makes the stochastic circuit simulator, referred to as PolySPICE, a compelling candidate for the tolerance study of reliability-critical electronic circuits

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

Abstract: ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results and demonstrates its strengths.

A Symmetric Electromagnetic-Circuit Simulator Based on the Extended Time-Domain Finite Element Method

Abstract: A symmetric hybrid electromagnetic-circuit simulator based on the extended time-domain finite element method (FEM) is presented for the simulation of microwave devices embedded with linear/nonlinear lumped circuits. The distributive portion of the device is modeled by the time-domain FEM to generate an electromagnetic subsystem, while the embedded lumped circuits are analyzed by a SPICE-like transient circuit solver to generate a circuit subsystem. A symmetric global system for both the electromagnetic and circuit unknowns is then established by combining the two fully discretized subsystems through coupling matrices to model their interactions. For active devices, the resulting global electromagnetic-circuit system usually includes nonlinear equations, and thus is solved by a solution algorithm carefully designed to handle nonlinearity. The proposed simulator significantly extends the capability of the existing time-domain finite element solver to model more complex and active devices such as microwave amplifiers. Numerical examples are presented to validate the algorithm and demonstrate its accuracy and applications.

Gate Oxide Wear-Out and Breakdown Effects on the Performance of Analog and Digital Circuits

Abstract: To investigate the impact of gate oxide degradation and breakdown (BD) on complimentary metal-oxide-semiconductor circuit functionality, an accurate description of the electrical characteristics of the stressed devices, which can be included in circuit simulators, is needed. In this paper, a description of the stressed device performance that considers, on the one hand, the variation of the channel current and, on the other, the increase in the gate current due to the oxide degradation and BD is presented, which is able to account for different levels of oxide damage. The parameters extracted from device experimental data have been introduced in a circuit simulator to evaluate the effect of the oxide degradation and BD on simple analog (current mirror) and digital [reset set (RS) latches] circuits. The impact of the increase in the gate leakage current and the variation of the conduction along the metal-oxide-semiconductor field-effect transistor channel due to the oxide degradation on the circuit performances has been separately analyzed.

SECS: A New Single-Electron-Circuit Simulator

Abstract: Downscaling of the devices of integrated circuits (ICs) has reached the verge of nanometer scale. On this scale, new phenomena of a quantum nature are starting to appear in ICs. The necessity of the development of new tools for studding the behavior of such circuits that take into account these phenomena is evident. For this reason, a new system for the design and simulation of single electron circuits called SECS has been developed. The operation of single electron circuits is based on the tunneling effect. The stochastic nature due to tunneling is incorporated in the simulation of single electron circuits using the Monte Carlo method. The novelty of the SECS system is that it provides the behavior of single electron circuits in an actual time scale, making thus easier and more complete the study of the phenomena that take place at an arbitrary single electron circuit.

Real-time HIL-simulation of power electronics

Abstract: In modern vehicles, electrical drives and power electronics are used to control a large variety of different applications To operate these components electronic control units have to be designed and tested To validate the software of the electronic control units hardware-in-the-loop simulation is a todaypsilas standard method Hardware-in-the-loop simulation always comprises a real-time simulation of the plant, including actuator and sensor models In case of an electronic circuit the plant consists of passive components like capacitors and inductors, usually assumed to be linear, and semi-conductors with nonlinear and discontinuous behavior The following paper suggests classification criteria and compares different methods for real-time simulations of electronic circuits considering switching events For evaluation theoretical considerations as well as simulation results are presented concerning differences in approaches

Redundancy reduction of IC models : by multirate time-integration and model order reduction

Abstract: Circuit simulation is an essential step within circuit design. Because of the increasing complexity of the Integrated Circuits, electronic companies need fast and accurate simulation software and there is a constant request at the companies to further improve the simulation software. Development of new, more advanced, transient simulation algorithms is an attractive way to increase the performance of this software. Mathematics is the basis to analyze the convergence properties. The objective of this PhD research is to increase the performance of Pstar, the in-house analog circuit simulator at Philips and now of NXP Semiconductors, while properties like accuracy and robustness are maintained. In particular the convergence and stability properties of newly developed multirate time-integration algorithms is studied. Usually circuit models are large systems of differential-algebraic equations that are derived from Kirchhoff’s conservation laws for currents and voltages and the constitutive relations for the electronic components. For a transient analysis one traditionally uses implicit time-integration schemes, like Backward Difference Formulae (BDF). All these schemes discretise the time on one time-grid. In contrast multirate algorithms use more than one time-grid and compute the slowly time-varying state elements only at coarsely distributed time-points, while the fastly time-varying state elements are computed at finer distributed timepoints. This makes a multirate algorithm potentially much faster for circuits with large low-frequency parts. There are many types of multirate timeintegration methods that may differ in the order of the slow and fast integration and the treatment of the interface variables. We used a direct extension of the BDF scheme combined with Lagrange interpolation of the same order. The standard theory for multistep methods does not hold anymore for multirate algorithms. Therefore we look at properties like stability and convergence in more detail. It turns out that the method is stable if the partitioned subsystems are individually stable and if the coupling is sufficiently weak. The discretisation error for a multirate method also contains an interpolation error due to the slow unknowns at the interface. This error component is not needed for ordinary multistep methods. It is possible to control this error by independent control of the coarse and fine macro and micro time-steps, respectively. The interpolation error and the coarse discretisation error is controlled by the macro stepsize, while the micro stepsize controls the fine discretisation errors for the fast state part. For multirate it is necessary to partitioning the system into a slow and a fast part. Therefore a part of the research is spent to the development and analysis of automatic partitioning algorithms. The underlying problem is a discrete optimisation problem, that can be handled by greedy-like methods. It is also possible to change the partitioning dynamically during the simulation, which is useful for moving active parts. All algorithms are implemented in Matlab; they work satisfactorily when tested for a variety of circuit models. Furthermore a multirate implementation including error control and dynamical partitioning is created in the circuit simulator Pstar itself. Besides multirate time-integration also model order reduction is studied, which transforms the large data models into smaller and simpler models, that still give the proper accuracy, but that are much cheaper to solve. Because IC models are nonlinear, nonlinear reduction techniques are considered in particular, like POD. In particular we focused on the problem to reduce the evaluation costs of these reduced models. A proper use of multirate and model order reduction is able to speed up transient simulation in general and is significantly faster (more than an order) for redundant circuit models, while the accuracy and robustness are maintained. Redundancy occurs if the state elements have many correlations, or if the sampled state signal has correlations in time.

Compact thermal model of a three-phase IGBT inverter power module

Abstract: A compact thermal model of a three-phase IGBT inverter power module utilised in most of variable speed drivers has been described in this paper. The compact thermal model equals to an electrical RC network model is assembled from thermal resistances and thermal capacitances so that it can be easily implemented in a circuit simulator. Transient thermal 3D finite element (FE) model of the IGBT module has been carried out using commercially available FLOTHERM software; the 3D simulation results are then utilised to extract the compact thermal network parameters of the IGBT power modular. Good agreement has been achieved between simulation and experimental measurement.

Practical chip-centric electro-thermal simulations

Abstract: Full-chip dynamic electro-thermal simulation is achieved by coupling a circuit simulator and a thermal solver. By letting both simulations run with their specific time-step, a higher computational efficiency is achieved. A scheduler synchronizes temperatures in the circuit simulator and dissipation patterns in the thermal solver on an dasiaas-necessarypsila basis. The 3D geometry for the thermal solver is generated automatically from the layout data-base and cross-referenced to the netlist to allow automatic extraction of power-dissipation from circuit simulations. In order to obtain realistic thermal responses for smart-power chips containing large driver transistors, it is essential to define the boundary conditions appropriately and account for package and PCB transients. To do so, the simulation domain is extended to cover the full package body, and uniform boundary conditions are defined to account for the thermal impedance of the PCB and for convection and radiation. Validation results are shown for the case of an SOIC package. Work is on-going on QFN and other power-packages.

Quantitative Estimation of Conducted Emission from an Inverter System

Abstract: This paper proposes a method for quantitative estimation of conducted emission from an inverter system, which helps the optimal design of EMI filters. The basic concept of the proposed method is the usage of a circuit simulator with detailed modeling of the components of the inverter system, i.e. passive devices, switching devices, and measurement instruments. The proposed method provides the conducted emission of the inverter in the form prescribed in CISPR 22, that is, the simulation results can be compared to the experiments directly. It is revealed that the simulation result agrees very well with the experiment with the error of ±6dB ranging from 150kHz to 5MHz. A great benefit from the proposed method is that the mode separation, differential and common, of the conducted emission becomes possible. Discussions and analyses are set forth in this paper with making full use of this benefit, which greatly makes the design of the EMI filter efficient.

3D strip meander delay line structure for multilayer LTCC-based SiP applications

Abstract: Recently, the timing control of high-frequency signals is strongly demanded due to the high integration density in three-dimensional (3D) LTCC-based SiP applications. Therefore, to control the skew or timing delay, new 3D delay lines will be proposed. For frailty of the signal via, we adopt the concept of coaxial line and proposed an advanced signal via structure with quasi coaxial ground (QCOX-GND) vias. We will show the simulated results using EM and circuit simulator.

EMC in Power Electronics

Abstract: Methodical approaches in EMC design are needed to significantly accelerate the development of power electronic devices and to reduce component costs. Major challenge is the handling of the high number of parameters necessary for predicting electromagnetic effects. This contribution describes the methods, tools and simplifications making this kind of investigation possible. Starting with modelling sources of interference the conducted spreading of interference in power electronic systems is simulated. The influence of component and line placement is added in a next step by using field simulation tools and implementing the results in circuit simulation. Examples and comparisons to measurement show the feasibility and efficiency of the proposed methods.

Sensitivity Degradation in a Tri-Band GSM BiCMOS Direct-Conversion Receiver Caused by Transient Substrate Heating

Abstract: An analysis of transient thermal substrate effects impairing the sensitivity of the DCS path in a tri-band GSM/DCS/PCS BiCMOS radio receiver is presented in this paper. A simple thermal model of the substrate is employed, enabling concurrent electrothermal circuit-substrate simulations within a standard analog circuit simulator. Simulation results obtained with this approach match very closely the measured data, and are used to predict the sensitivity of different circuit layout configurations to thermal gradients in the substrate. Following the guidelines suggested by these analyses, a redesigned version of the receiver displays a sensitivity improvement of 2 dB to 4 dB.

Application of negative group delay active circuits to reduce the 50% propagation Delay of RC-line model

Abstract: This paper presents a new method developed to reduce the propagation delay by using a negative group delay (NGD) active circuit. Analytical expressions are proposed to demonstrate the validity of our approach in the case of an RC-transmission line model. The synthesis method of NGD circuits versus the line length is detailed. For a 0.5 Gbit/s digital signal and a 2-cm-long RC-line model, time-domain simulations carried out with a high-frequency circuit simulator showed that the 50% propagation delay was reduced by 94%. Finally, potential applications of this method to compensate for time delays in different interconnect configurations (VLSI, package, on-chip, long-line, ...) are discussed.

An Efficient Implementation of the Agrawal Model for Lightning-Induced Voltage Calculations Using Circuit Simulation Software

Abstract: One of the popular, simple, and accurate field-to-wire coupling models for studying transmission-line lightning interaction is the Agrawal model . In this model, the coupling mechanisms are represented by distributed sources along the line, wherein each distributed source is due to the horizontal component of the illuminating electric field at that point on the line. These sources give rise to the propagating scattered voltage along the line, while the total voltage at any instant at a given point along the line is the sum of scattered voltage and the voltage at that point due to the illuminating vertical component of the electric field. There is a difficulty in applying the Agrawal model with the built-in transmission-line models of various circuit simulation software such as the Alternate Transients Program-Electromagnetic Transients Program , PSpice , Simpow , PSS/E , etc., as the voltage source due to the horizontal component of the electric field in the Agrawal model is in series with the line impedance , and not in between two transmission-line segments. In this paper, a simple circuit approach for efficient implementation of the Agrawal model using any circuit simulation software that has built-in transmission-line models is proposed.

Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator

Abstract: An evolutionary algorithm is used to design digital circuits at the transistor level. In particular, various static CMOS circuits with up to four inputs were evolved. The increase in the complexity of evolved circuits wrt existing circuits evolved at the transistor level is primarily caused by two phenomena: the usage of a specialized circuit simulator and restriction of the search space. Because we restricted the search space to the set of "reasonable designs" we could employ imperfect, but very fast circuit simulation. The usage of proposed simulator allowed exploring more candidate designs than a conventional Spice-based approach. However, in some cases, an incorrect behavior was detected after validation of evolved circuits using Spice simulator.

Lumped and Distributed Parameter SPICE Models of TE Devices Considering Temperature Dependent Material Properties

Abstract: Based on simplified one-dimensional steady-state analysis of thermoelectric phenomena and on analogies between thermal and electrical domains, we propose both lumped and distributed parameter electrical models for thermoelectric devices. For lumped parameter models, constant values for material properties are extracted from polynomial fit curves evaluated at different module temperatures (hot side, cold side, average, and mean module temperature). For the case of distributed parameter models, material properties are calculated according to the mean temperature at each segment of a sectioned device. A couple of important advantages of the presented models are that temperature dependence of material properties is considered and that they can be easily simulated using an electronic simulation tool such as SPICE. Comparisons are made between SPICE simulations for a single-pellet module using the proposed models and with numerical simulations carried out with Mathematica software. Results illustrate accuracy of the distributed parameter models and show how inappropriate is to assume, in some cases, constant material parameters for an entire thermoelectric element.

Neuro-space mapping technique for semiconductor device modeling

Abstract: This paper presents an application of the space mapping concept in the modeling of semiconductor devices. A recently proposed device modeling technique, called neuro-space mapping (Neuro-SM), is described to meet the constant need of new device models due to rapid progress in the semiconductor technology. Neuro-SM is a systematic method allowing us to exceed the present capabilities of the existing device models. It uses a neural network to map the voltage and current signals between an existing device model (coarse model) and the actual device behavior (fine model), such that the mapped model becomes an accurate representation of the new device. An efficient training method based on analytical sensitivity analysis for such mapping neural network is also addressed. The trained Neuro-SM model can retain the speed of the existing device model while improving the model accuracy. The benefit of the Neuro-SM method is demonstrated by examples of SiGe HBT and GaAs MESFET modeling and use of the models in harmonic balance simulation.

Modeling multilayer power distribution network by systematically incorporating via and cavity models

Abstract: A closed-form expression for via barrel-plate capacitances is derived. This results in a more accurate equivalent circuit model for decoupling capacitors including both parasitic inductances and via capacitances. Multilayer power distribution network (PDN) are then analyzed by incorporating the circuit models of both vias and parallel plane pair. Circuit simulator is used to evaluate the coupling properties among various locations in the multilayer PDN structures.

Circuit coupled simulation of a claw-pole alternator by a temporary linearization of the 3D-FE model

Abstract: During the final stage in the design of electrical machines adequate models are required to predict the behavior at given points of operation. Due to its irreducible 3D flux path structure and the connected bridge rectifier, the claw pole generator is a challenging field-circuit coupled system. It can be solved either by permeance models, state space models or numerically strong coupled formulations within a Finite Element Analysis (FEA). Alternatively, a numerically weakly coupled method is presented in this paper. A temporary lumped parameter representation of the alternator seen from stator terminals is extracted from the Jacobian matrix of the linearized FE model. This lumped parameter representation of the machine is then incorporated into a circuit simulator based on the modified nodal analysis (MNA).

A circuit model for ESD performance analysis of printed circuit boards

Abstract: This paper provides a SPICE-compatible circuit model for characterizing electrostatic discharge (ESD) clamping performance of protection devices mounted on printed circuit boards (PCBs). An equivalent circuit model for a commercial ESD generator is introduced and a simulation methodology of an ESD protection device with non-linear resistance characteristic using voltage controlled current source is described. These models combined to create a full circuit model with a PCB model in a SPICE-like circuit simulator. Comparison results between the simulated and measured are presented to verify the accuracy of the proposed circuit model. A trade-off analysis between the ESD clamping performance and signal integrity with the ESD protection device in high-speed applications is also presented as a case study.

Analysis of systematic variation and impact on circuit performance

Abstract: Yield loss due to process variations can be classified as catastrophic or parametric. Parametric variations can further be random or systematic in nature. Systematic parametric variations are being projected as a major yield limiter in sub- 65nm technologies. Though several models exist to describe process-induced parametric effects in layouts, there is no existing design methodology to study the variational (across process window) impact of all these effects simultaneously. In this paper, we present a methodology for analyzing multiple process-induced systematic and statistical layout dependent effects on circuit performance. We describe physical design models used to describe four major sources of parametric variability - lithography, stress, etch and contact resistance - and their impact on device properties. We then develop a methodology to determine variability in circuit performance based on integrating the above device models with a circuit simulator like SPICE. A circuit simulation engine for 45nm SOI devices is implemented, which shows the extent of the impact of layout-dependent systematic variations on circuit parameters like delay and power. Based on the analysis, we demonstrate that all systematic effects need to be simultaneously included to match the hardware data. We believe a flow that is capable of understanding process-induced parametric variability will have major advantages in terms of improving physical design and yield in addition to reducing design to hardware miscorrelations and advantages in terms of diagnosis and silicon debug.

Optimization of the NMOS and PMOS gate cross-connected rectifier for RF power extraction in RFID applications

Abstract: The NMOS and PMOS gate cross-connected bridge rectifier has been proved an efficient way to realize the power extraction for passive RFID applications. In this paper, such a rectifier has been analyzed from its different state during the period of the RF input signal. The calculations reveal the essence of this circuit and some useful relations are calculated and plotted by MATLAB. With these relations this circuit can be easily optimized. It agrees very well with the results simulated by a circuit simulator such as Cadence but the optimization and design time-consumption is greatly reduced. For much higher output voltage the multi-stages structure may be applied to keep the basic rectifiers of each stage in their most efficient operation point.

High Frequency Circuit Simulator based on finite integration technology

Abstract: This paper provides the design and realization of high frequency circuit simulator (HFCS) which is based on the Finite Integration Technology. For vilification, the cold-test characteristics of two actual helical slow wave structures have been calculated and the results were found to be consistent with those of MAFIA simulation with same mesh density.

Design of a Compact low-pass Filter with Wide Stopband

Abstract: This paper presents a novel low-pass filter (LPF) with sharp rejection, wide stopband and compact size, which are realized by the defected ground structure (DGS) and the defected microstrip structure (DMS). The equivalent circuit model is proposed and the circuit parameters are extracted by the circuit simulation software. The parameters measured are 3 dB cutoff frequency f c of 5.2 GHz, the insertion loss less than 0.5 dB from DC to 4.0 GHz and S21 less than −20 dB within the wide stopband from 6 GHz to 16 GHz. The results of the circuit optimization agree well with those of the full wave simulation and the measured ones, which validate the effectiveness of the equivalent circuit model. The size of the proposed LPF is decreased compared with normal LPF. This LPF can be applied in rectennas to eliminate high order harmonics.

Analysis of oscillator injection locking by harmonic balance method

Abstract: A new approach to analyze injection locking mode of oscillators under small external excitation is proposed. The proposed approach exploits existence conditions of the solution of HB linear system with degenerate matrix. The method allows one to obtain the locking range for an arbitrary oscillator circuit with an arbitrary periodic injection waveform. The approach can be easily implemented into a circuit simulator. Examples are given to confirm the correctness of the new approach.