Showing papers on "Electronic circuit simulation published in 2012"

Behavioral Average Modeling and Equivalent Circuit Simulation of Switched Capacitors Converters

Abstract: A generic behavioral average circuit model of a switched capacitor converter (SCC) is proposed and demonstrated by a unity conversion SCC The model is based on the average currents concept and can be used to calculate or simulate the average values of the SCC variables such as output voltage, capacitor voltages, and subcircuit currents The model is valid for all operational ranges of an SCC (complete, partial, and no charge) and is compatible with any circuit simulator that includes dependent sources Excellent agreement was found between full switched-circuit simulation, average simulation by proposed model, and experimental results

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis

Abstract: Design of hybrid circuits and systems based on CMOS and nano-device requires rethinking of fundamental circuit analysis to aid design exploration. Conventional circuit analysis with modified nodal analysis (MNA) cannot consider new nano-devices such as memristor together with the traditional CMOS devices. This paper has introduced a new MNA method with magnetic flux (Φ) as new state variable. New SPICE-like circuit simulator is thereby developed for the design of hybrid CMOS and memristor circuits. A number of CMOS and memristor-based designs are explored, such as oscillator, chaotic circuit, programmable logic, analog-learning circuit, and crossbar memory, where their functionality, performance, reliability and power can be efficiently verified by the newly developed simulator. Specifically, one new 3-D-crossbar architecture with diode-added memristor is also proposed to improve integration density and to avoid sneak path during read-write operation.

New Trends for the Nonlinear Measurement and Modeling of High-Power RF Transistors and Amplifiers With Memory Effects

Abstract: Power amplifier (PA) behavior is inextricably linked to the characteristics of the transistors underlying the PA design. All transistors exhibit some degree of memory effects, which must therefore be taken into account in the modeling and design of these PAs. In this paper, we will present new trends for the characterization, device modeling, and behavioral modeling of power transistors and amplifiers with strong memory effects. First the impact of thermal and electrical memory effects upon the performance of a transistor will be revealed by comparing continuous wave and pulsed RF large-signal measurements. Pulsed-RF load-pull from the proper hot bias condition yields a more realistic representation of the peak power response of transistors excited with modulated signals with high peak-to-average power ratio. Next, an advanced device modeling method based on large-signal data from a modern nonlinear vector network analyzer instrument, coupled with modeling approaches based on advanced artificial neural network technology, will be presented. This approach enables the generation of accurate and robust time-domain nonlinear simulation models of modern transistors that exhibit significant memory effects. Finally an extension of the X-parameter (X-parameter is a trademark of Agilent Technologies Inc.) behavioral model to account for model memory effects of RF and microwave components will be presented. The approach can be used to model hard nonlinear behavior and long-term memory effects and is valid for all possible modulation formats for all possible peak-to-average ratios and for a wide range of modulation bandwidths. Both the device and behavioral models have been validated by measurements and are implemented in a commercial nonlinear circuit simulator.

A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors

Abstract: A compact model for tunneling field-effect-transistors (TFETs) is presented. The model includes a band-to-band tunneling (BTBT) current module and a terminal charge module. TCAD simulations show that the model describes TFETs currents and capacitances accurately. The model is implemented into a circuit simulator and used to simulate TFETs logic circuits and SRAMs. Unique features in TEFTs including large overshoot during switching, long delay and uni-directional conduction are demonstrated.

Method and system for implementing parallel execution in a computing system and in a circuit simulator

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

An Optimized Device Sizing of Analog Circuits using Particle Swarm Optimization

Abstract: Problem statement: Day by day more and more products rely on analog circuits to improve the speed and reduce the power consumption(Products rely on analog circuits to improve the speed and reduce the power consumption day by day more and more.). For the VLSI implementation analog circuit design plays an important role. This analog circuit synthesis might be the most challenging and time-consumed task, because it does not only co nsist of topology and layout synthesis but also of component sizing. Approach: A Particle Swarm Optimization (PSO) technique for the optimal design of analog circuits. Analog signal processing finds many applications and widely uses OpAmp based amplifiers, mixers, comparators. and filters. Results: A two-stage opamp (Miller Operational Trans-conductance Amplifier (OTA)) is considered for the synthesis that satisfies certain design specifications. Performance has been evaluated with the Simulation Program with Integrated Circuit Emphasis (SPICE) circuit simulator until optimal si zes of the transistors are found. Conclusion: The output of the simulation for the two-stage opamp sh ows that the PSO technique is an accurate and promising approach in determining the device sizes in an analog circuit.

Calculation of Lightning-Induced Overvoltages on Overhead Lines Based on DEPACT Macromodel Using Circuit Simulation Software

Abstract: One of the simple and accurate methods for calculating the lightning-induced overvoltages is based on the Agrawal et al. held-to-wire model, in which the coupling mechanisms are presented by distributed voltage sources along the lines. There is a difficulty in calculating the lightning-induced overvoltages with the built-in transmission line models or other circuit elements of various circuit simulation software such as the PSCAD/EMTDC, EMTP/ATP, PSpice, etc., as the distributed voltage sources due to the horizontal component of the electric held caused by the lightning channel are in series with the line and not in between two transmission-line segments. In this paper, a simple circuit approach for efficient calculation of the lightning-induced overvoltages using the circuit simulation software is proposed. The delay extraction passive compact circuit (DEPACT) macromodel is applied and the transmission line is divided into a cascade of DEPACT subnetworks which can be represented by a cascade of two lossless transmission lines and a lossy network. By assuming the incident held only couples with the lossless transmission line sections, the distributed equivalent voltage sources due to the horizontal component of the incident electric held can be lumped at the termination of the lines, which makes it convenient for the engineering technologist to calculate the lightning-induced overvoltages in various circuit simulation software. Furthermore, in order to treat the nonlinear element such as metal oxide arrester (MOA) directly, the DEPACT macromodel is improved and the macromodel of multiconductor transmission lines excited by the external electromagnetic held can be solved in the actual phase domain instead of in the modal domain. Compared with the existing method for calculating the lightning-induced overvoltages, the benefit of the proposed algorithm is that it can be used to calculate the transients of the transmission line more efficiently. Considering the PSCAD/EMTDC is a powerful simulation software which providing lots of equipment models in power system, such as transformer, generator, and protection modules et al., an implementation procedure in the PSCAD/EMTDC is provided in this paper, which makes it more convenient for the electrical engineering technologists to analyze the lightning-induced overvoltages problems in the power system. Several numerical calculations of the line transient responses are provided and the CPU time is compared, which indicate the validity and efficiency of the algorithm proposed in the paper. At last, this algorithm is applied to analyze the influence of the ground wire and the MOA on the lightning-induced overvoltages of the overhead lines.

Generic average modeling and simulation of the static and dynamic behavior of Switched Capacitor Converters

Abstract: A generic behavioral average circuit model of a Switched Capacitor Converter (SCC) is proposed and verified. The model is based on the average currents concept and assumes that each of the SCC subcircuits can be described or approximated as a first order network. The model can be used to calculate or simulate the average static, dynamic and small signal responses of the SCC. The model is valid for all operational modes of a SCC (complete, partial and no charge) and is compatible with any circuit simulator that includes dependent sources. Excellent agreement was found between the behavior of the proposed average model, full circuit simulation, and experimental results.

From Layout Directly to Simulation: A First-Principle-Guided Circuit Simulator of Linear Complexity and Its Efficient Parallelization

Abstract: In this paper, guided by electromagnetics-based first principles, the authors develop a transient simulator that allows for the simulation of an integrated circuit including both nonlinear devices and the layout of the linear network in linear complexity. The proposed circuit simulator rigorously captures the coupling between nonlinear circuits and the linear network. In addition, it bypasses the step of circuit extraction, producing a resistor-inductor-capacitor representation of the linear network without any numerical computation. Moreover, it permits an almost embarrassingly parallel implementation on a many-core computing platform, and hence enabling linear speedup. Application to die-package co-simulation as well as very large-scale on-chip circuits involving over complementary metal-oxide semiconductor transistors and interconnects having hundreds of millions of unknowns has demonstrated the superior performance of the proposed first-principle-guided circuit simulator.

MATLAB modeling and simulation of photovoltaic modules

Abstract: In this paper a modeling method is investigated that finds the non-linear equation parameters of a photovoltaic (PV) module in order to obtain the desired PV model using any circuit simulator. This modeling method adjusts the I–V curve at three remarkable points: the open circuit voltage, the short circuit current, and the maximum power point [1]. Three models are realized using this technique namely, the single-diode model, the two-diode model, and the three-diode model. The evaluation study of the accuracy of these three models showed relative errors ranging from 32% to 50%. Further, this technique is improved by adjusting the I–V curve at more than three points depending on the number of unknowns to be found for each model, which showed a reduction in the relative error ranging from 0.37% to 38%. Finally, a study of the parameters obtained from the modeling algorithm on the performance of the proposed single-diode model is presented.

Parallel Circuit Simulation: A Historical Perspective and Recent Developments

Abstract: The ability to predict circuit performance through simulation is at the core of any design process; it makes the implementation of complex integrated circuits technically feasible and economically viable while relaxing any heavy need for prototyping. Transistor-level circuit simulation is a fundamental computer-aided design technique that enables the design and verification of an extremely broad range of integrated circuits. With the proliferation of modern parallel processor architectures, leveraging parallel computing becomes a necessity and also an important avenue for facilitating large-scale circuit simulation. Parallel Circuit Simulation: A Historical Perspective and Recent Developments presents an in-depth discussion on parallel transistor-level circuit simulation algorithms and their implementation strategies on a variety of hardware platforms. While providing a rather complete perspective on historical and recent research developments, it also highlights key challenges and opportunities in developing efficient parallel simulation paradigms.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Abstract: Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

A Behavioral Circuit Model of Active-Matrix Liquid Crystal Displays for Optical Response Simulation

Abstract: We propose a behavioral circuit model to precisely predict optical responses of an active-matrix liquid crystal (LC) display (LCD) using a patterned vertical alignment (PVA) mode To get more accurate simulation results, we propose two LC groups with different time constants for a pixel after observing the LCD pixels by using a high-speed camera In addition, we include a time-delay concept into our behavioral model for brightening or rising transitions We describe the behavior of the PVA-LCD by using the analog hardware description language Verilog-A We simulate the PVA-LCD panel by importing the behavioral circuit model in the circuit simulator SmartSPICE The simulation results of the transient optical responses show excellent matches with the measurement ones

KLU sparse direct linear solver implementation into NGSPICE

Abstract: The simulation of large digital and mixed-signal integrated circuits is one of the challenges of the electronics design automation industry. In this work, a fast linear solver, KLU, is implemented into NGSPICE circuit simulator and its performances have been verified on standard netlists.

Circuit Design-Oriented Stochastic Piecewise Modeling of the Postbreakdown Gate Current in MOSFETs: Application to Ring Oscillators

Abstract: A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemented in circuit simulation tools. Device level characterization of the BD mechanism is presented, which is the base for model parameter extraction. The model has been introduced in a circuit simulator to show its suitability for evaluation of the BD effect in circuits and their reliability, taking ring oscillators as example.

A multi-physics simulation technique for integrated MEMS

Abstract: We have developed a multi-physics simulation platform for microelectromechanical systems (MEMS) on a spice-based circuit simulator (LTspice) and by interpreting the analytical models for electromechanical components such as electrostatic parallel-plate actuator, viscoelastic spring, and mechanical anchor by using behavioral current/voltage sources The Kernel solver for the mechanical equation of motion (EOM) has been programmed by simply using the integral function of the LTspice mathematic library Simulation capability has been extended to and tested against the electrostatic digital torsion mirror device integrated with CMOS level shifter circuit

Design Methodology of Large-Scale Thermoelectric Generation: A Hierarchical Modeling Approach

Abstract: A thermoelectric generation system (TEGS) used in the practical industry of waste heat recovery consists of the fluidic heat sources, the external load circuitry, and many thermoelectric modules (TEMs) connected as a battery bank. In this paper, a system-level model is proposed to seamlessly integrate the complete fluid-thermal-electric-circuit multiphysics behaviors in a single circuit simulator using electrothermal analogy. First, a quasi one-dimension numerical model for the thermal fluids and their nonuniform temperature distribution as the boundary condition for TEMs is implemented in simulation program with integrated circuit emphasis (SPICE)-compatible environment. Second, the electric field calculation of the device-level model is upgraded to reflect the resistive behaviors of thermoelements, so that the electric connections among spatially distributed TEMs and the load circuitry can be freely combined in the simulation. Third, a hierarchical and TEM-object oriented strategy are developed to make the system modeling as well as the design scalable, flexible, and programmable. To validate the proposed system model, a TEGS, including eight TEMs is constructed. Through comparisons between simulation results and experimental data, the proposed model shows sufficient accuracy so that a straightforward cooptimization of the entire TEGS of large scale can be carried out.

Circuit models for ESD-generator-cable field coupling configurations based on measurement data

Abstract: Accurate and flexible modeling of field coupling from ESD sources to cables or PCB traces (indirect ESD) is important for immunity estimations. Accurate circuit models can be obtained by applying approximations techniques to measurement data in frequency domain. In this paper an accurate ESD generator model is extended to model ESD coupling behavior for the ESD generator to a cable setup. The new model can be used for simulation of arbitrary load conditions, for both direct and indirect discharge. The model represents the individual characteristics of an ESD generator without applying complex 3D field simulation. It allows computation of the coupled voltages over linear or nonlinear termination using a circuit simulator.

Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification

Abstract: In this contribution a novel formal methodology for equivalence checking of analog circuits is proposed. In order to prove the behavioral equivalence of two circuit implementations such as a transistor netlist and a corresponding behavioral model, guaranteed coverage of the complete reachable state space for each of the two circuits under verification is obtained by an efficient input stimuli generation algorithm. These input stimuli are processed by a conventional circuit simulator to obtain simulation results covering each system's complete dynamic behavior. By automatically comparing the simulation results using specific error measures, the level of equivalence of both systems is determined. Simulation by complete state space-covering input stimuli guarantees the equivalence checking results to be sound for every possible state and input stimulus of the circuits under verification, which allows safe application of analog behavioral models in hierarchical AMS system simulation flows. The application to example circuits shows the feasibility of the approach.

Adaptive Wavelet-Based Method for Simulation of Electronic Circuits

Abstract: In this paper we present an algorithm for analog simulation of electronic circuits involving a spline Galerkin method with wavelet-based adaptive refinement. Numerical tests show that a first algorithm prototype, build within a productively used in-house circuit simulator, is completely able to meet and even surpass the accuracy requirements and has a performance close to classical time-domain simulation methods, with high potential for further improvement.

MATLAB Modeling and Simulation of Photovoltaic Modules

Abstract: In this paper a modeling method is investigated that finds the non-linear equation parameters of a photovoltaic (PV) module in order to obtain the desired PV model using any circuit simulator. This modeling method adjusts the I-V curve at three remarkable points: the open circuit voltage, the short circuit current, and the maximum power point [1]. Three models are realized using this technique namely, the single-diode model, the two-diode model, and the three-diode model. The evaluation study of the accuracy of these three models showed relative errors ranging from 32% to 50%. Further, this technique is improved by adjusting the I-V curve at more than three points depending on the number of unknowns to be found for each model, which showed a reduction in the relative error ranging from 0.37% to 38%.

Optimizing method of analogue integrated circuit design

Abstract: The invention relates to an optimizing method of an analogue integrated circuit design, belonging to the field of automation of integrated circuit designs. The optimizing method comprises the following steps of: inputting a circuit network table, performance design indexes and a performance test circuit; determining a target optimization value of each index item of circuit optimization based on an equation, an optimization value of each index item of the circuit optimization based on a circuit simulator after eliminating the self parasitic effect of a device, and an optimization value of eachindex project of the circuit optimization based on the circuit simulator after taking the physical connection parasitic effect of the circuit into account; executing the circuit optimization based onthe equation; executing the circuit optimization based on the circuit simulator; and carrying out the circuit optimization based on the circuit simulator. According to the optimizing method of the analogue integrated circuit design disclosed by the invention, the reliability of circuit evaluation is improved, and the optimization speed is increased, thus the zone times between the circuit design and the physical design is reduced, the design efficiency is improved and the design cycle is shortened.

A new approach to deriving packaging system statistical eye diagram based on parallel non-linear transient simulations using multiple short signal bit patterns

Abstract: The eye diagram simulation is very important for checking the signal quality of channels in electronic packaging systems. Most existing simulation tools for creating eye diagram are based on convolution using a single-step response of the channel and require that the I/O devices are modeled as linear time-invariant circuits. However, I/O devices do contain nonlinear elements and some applications have strongly nonlinear I/O devices. We need an alternative eye diagram simulation methodology to simulate these non-linear applications. In this paper, we propose a new approach to deriving the packaging system statistical eye diagram based on nonlinear transient simulations. This is achieved by taking advantage of the ready availability of multi-core networked computers and breaking the bit patterns into many short signal bit patterns and running these simulations in parallel. This can be done with any transient circuit simulator. This approach gives a practical way to overcome the time required to run the more compute intensive non-linear transient simulations. A major advantage of this approach is the capability to include the nonlinear effect of the actual I/O devices. The statistical eye diagram and the BERT scan eye diagram by the proposed approach includes the non-ideal channel characteristics including inter-symbol interference (ISI), the crosstalk from nearby aggressor channels, the random jitter, and duty cycle distortion. The proposed approach is illustrated with the simulation an actual channel from an IBM server. The statistical eye diagram is compared between this approach and the commonly used linear convolution methods.

Signal integrity: Efficient, physics-based via modeling: Integration of striplines

Abstract: In the first article of this series, principles and methods of physics-based via modeling were discussed. It was shown how the electromagnetic behavior of vias can be captured by an equivalent circuit based modeling approach that describes all relevant full-wave effects. In this follow-up article, the authors present an approach to integrate striplines into the physics-based via model. The striplines can be located at any layer of the stackup and they may constitute both single and multiconductor transmission lines. The integration of striplines extends the via representation to a full, efficient interconnect model of, for instance, printed circuit board signal links. An intuitive integration approach at a circuit simulator level and application examples are discussed in this article as well.

Multi-level reliability simulation for IC design

Abstract: CMOS IC design is challenged by the ever-increasing reliability issues, demanding highly accurate and efficient reliability simulation methodology. This paper presents multi-level solutions for reliability prediction in digital and analog design, including (1) device-level long-term aging models that capture unique operation patterns in digital and analog design, (2) circuit-level simulation method for analog reliability analysis, and (3) gate-level reliability simulation for large-scale digital designs. These solutions are integrated into IC design tools, helping diagnose critical conditions for circuit failure and enable adaptive design for resilience.

Extraction Method for Substrate-Related Components of Vertical Junctionless Silicon Nanowire Field-Effect Transistors and Its Verification on Radio Frequency Characteristics

Abstract: In this paper, we propose a radio-frequency (RF) model and parameter extraction method for vertical junctionless silicon nanowire (VJL SNW) field-effect transistors (FETs) using three-dimensional (3D) device simulation. We introduce the substrate-related components such as the substrate resistance (Rsub) and drain-to-substrate capacitance (Csub), and evaluate the RF performance such as ft, fmax, gate input capacitance, and transport time delay. A quasi-static (QS) RF model has been used in simulation program with integrated circuit emphasis (SPICE) circuit simulator to simulate VJL SNW FETs with RF parameters extracted from 3D device simulated Y-parameters. We confirmed the validity of our RF model by the well-matched results between HSPICE and 3D device simulation in terms of the Y-parameters and the S22-parameter up to 100 GHz.

A Circuit Model for Vertical Multilayer Transitions in Coplanar Waveguide Technology

Abstract: A circuit model for vertical transitions between difierent coplanar waveguide systems using via-holes is presented. The model is directly extracted from the geometry of the transition using closed expressions. Additionally, it can be used to flnd suitable initial dimensions for the transition in a circuit simulator, thereby greatly reducing the efiort spent on subsequent electromagnetic simulations. To test the validity of the developed model, it is applied to a variety of situations involving a wide range of stack heights, dielectric constants, and transmission line geometry values. These situations cover most of the relevant broadband vertical transitions used in practical PCB and LTCC designs. Comparative analysis of the circuit model and electromagnetic simulations yields good agreement in all analyzed situations. Experimental assessment of the model is also provided for some of the transitions that were built and characterized in a back-to- back conflguration.

Accurate loss model for DC-DC buck converter including non-linear driver output characteristics

Abstract: In this paper an accurate loss model is proposed for synchronous DC-DC buck converters. The proposed method uses non-linear driver output stage model to accurately compute rise and fall times of MOSFET voltage and current waveforms to allow accurate calculation of switching loss. Transistor level simulations using Cadence Spectre circuit simulator and experimental results are used to demonstrate the accuracy of the driver model and the loss model at various input voltage, load current and switching frequency conditions.

Verilog-a compact semiconductor device modelling and circuit macromodelling with the QucsStudio-ADMS “turn-key” modelling system

Abstract: The Verilog-A “Analogue Device Model Synthesizer” (ADMS) has in recent years become an established modelling tool for GNU General Public License circuit simulator development. Qucs and ngspice being two examples of open source circuit simulators that use ADMS. This paper presents a “turn-key” compact device modelling and circuit macromodelling system based on ADMS and implemented in the QucsStudio circuit design, simulation and manufacturing environment. A core feature of the new system is a modelling procedure which does not require users to manually patch the circuit simulator C++ code. At the start of a QucsStudio simulation the software automatically detects any changes in Verilog-A model code, re-compiling and dynamically linking the modified code to the body of the QucsStudio code. The inherent flexibility of the “turn-key” system encourages rapid experimentation with analogue and RF compact device models. In this paper QucsStudio “turn-key” modelling is illustrated by the design of a single stage RF amplifier circuit.

Fast 3D thermal simulation of power module packaging

Abstract: This paper presents a thermal model that uses a Fourier series solution to the heat equation to carry out transient 3D thermal simulation of power device packaging. The development and implementation of this physics-based method is described. The method is demonstrated on a stacked 3D multichip module. The required aspects of 3D heat conduction are captured successfully by the model. Compared with previous thermal models presented in literature, it is fast, accurate and can be easily integrated with an inverter circuit simulator to model realistic converter load cycles. Copyright © 2012 John Wiley & Sons, Ltd.