Showing papers on "Electronic circuit simulation published in 2021"

Stim: a fast stabilizer circuit simulator

Abstract: This paper presents ``Stim", a fast simulator for quantum stabilizer circuits. The paper explains how Stim works and compares it to existing tools. With no foreknowledge, Stim can analyze a distance 100 surface code circuit (20 thousand qubits, 8 million gates, 1 million measurements) in 15 seconds and then begin sampling full circuit shots at a rate of 1 kHz. Stim uses a stabilizer tableau representation, similar to Aaronson and Gottesman's CHP simulator, but with three main improvements. First, Stim improves the asymptotic complexity of deterministic measurement from quadratic to linear by tracking the {\em inverse} of the circuit's stabilizer tableau. Second, Stim improves the constant factors of the algorithm by using a cache-friendly data layout and 256 bit wide SIMD instructions. Third, Stim only uses expensive stabilizer tableau simulation to create an initial reference sample. Further samples are collected in bulk by using that sample as a reference for batches of Pauli frames propagating through the circuit.

Design and Verification of SFQ Cell Library for Superconducting LSI Digital Circuits

Abstract: We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2 Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current ( IC ), bias current ( Ibias ), and inductance satisfied minimal margin requirements. Critical margins of IC and Ibias were then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC . The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.

Analysis of Electrothermal Effects in Devices and Arrays in InGaP/GaAs HBT Technology

Abstract: In this paper, the dc electrothermal behavior of InGaP/GaAs HBT test devices and arrays for power amplifier output stages is extensively analyzed through an efficient simulation approach. The approach relies on a full circuit representation of the domains, which accounts for electrothermal effects through the thermal equivalent of the Ohm’s law and can be solved in any commercial circuit simulator. In particular, the power-temperature feedback is described through an equivalent thermal network automatically obtained by (i) generating a realistic 3-D geometry/mesh of the domain in the environment of a numerical tool with the aid of an in-house routine; (ii) feeding the geometry/mesh to FANTASTIC, which extracts the network without performing simulations. Nonlinear thermal effects adversely affecting the behavior of devices/arrays at high temperatures are included through a calibrated Kirchhoff’s transformation. For the test devices, the thermally-induced distortion in I–V curves is explained, and the limits of the safe operating regions are identified for a wide range of bias conditions. A deep insight into the electrothermal behavior of the arrays is then provided, with particular emphasis on the detrimental nonuniform operation. Useful guidelines are offered to designers in terms of layout and choice of the ballasting strategy.

Design of Amplifier for Wearable Human ECG Sensor with Low Power and Low Noise

Abstract: Electrocardiograph (ECG) data is an important index to determine the human heart state, which helps diagnose heart disease in an early stage. Since the ECG signal is instantaneous, it is important to make the ECG signal collector wearable and have good battery life. The wearable ECG devices need to have certain properties like interference suppression ability of acquired signal, low power consumption, low noise, and high integration, putting forward crucial requirements for the design of the amplifier. To meet the properties, the front-end analog processing circuit with interface input buffer stage structure and post-amp structure was proposed here, which has the characteristics of small size, low power consumption, low input referred noise, fair common-mode rejection ratio, and high input impedance. Besides, as one of the industrial-grade circuit simulation software, LTspice was used to design the circuit structure and analyze the corresponding performance. According to the circuit design and simulation testing, it turned out that the circuit in this work can be quite simple, and all the performance indexes met the practical demands. The frequency range was 0.1Hz∼100Hz, the voltage was 1.2V, the differential gain was 40.37dB, the total integrated input-referred noise was 3.48uVrms, and the total power consumption was 1.75uW. In summary, our data indicate that the ECG device we design is small enough to be wearable and has low power consumption.

Modeling Power GaN-HEMTs Using Standard MOSFET Equations and Parameters in SPICE

Abstract: The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL 3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL 3 model. The advantage of the proposed approach to use the MOSFET LEVEL 3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL 3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.

Behavioral Modeling of Complex Magnetic Permeability With High-Order Debye Model and Equivalent Circuits

Abstract: In this article, a systematic procedure to derive equivalent circuit networks accurately reproducing the frequency response of the input impedance of magnetic cores in a broad frequency range is presented. The proposed procedure foresees to represent the effective complex permeability spectra of a magnetic core (i.e., the permeability resulting from the superposition of intrinsic material properties and effects due to structural features of the core) by a high-order Debye series expansion, which is subsequently synthesized into suitable Foster and Cauer networks. Such networks can be implemented in any circuit simulator, and are particularly favorable for time-domain transient simulation since they can be easily combined with hysteresis models. Two nanocrystalline tape-wound cores and a commercial bulk current injection probe are used as test cases to prove the effectiveness of the proposed method both in terms of accuracy and ease of implementation.

High-Frequency Modelling of Electrical Machine Windings Using Numerical Methods

Abstract: This paper presents a method for predicting high-frequency behavior of rotating electrical machines. An approach using the Finite Elements (FE) method coupled with a circuit simulator is utilized to obtain the machine common-mode and differential-mode impedances over the frequency range of interest. The machine geometry, winding configuration and material characteristics are the input for the proposed process. 2D electrostatic FE simulation is used to obtain the capacitive couplings while a magnetodynamic FE approach is used to obtain the frequency-dependent resistances and inductances. These parameters are used in an equivalent circuit that represents the machine stator winding layout. A Permanent Magnet Synchronous Machine (PMSM) is used as a case study machine to implement the method. The agreement between the simulated model and experimental results is presented assessing the accuracy of the method.

Experimental Verification of Moat Design and Flux Trapping Analysis

Abstract: Soft defects caused by flux quanta not captured by moats during superconductor integrated circuit cooldown are known to degrade circuit performance. However, haphazard or random moat placement does not necessarily improve circuit performance and may even degrade it. Under the IARPA SuperTools program we have both developed numerical simulation tools to extract simulation models of circuit structures in the presence of trapped fluxons and designed experiments to measure the probability of flux trapping in moats and the coupling of such trapped flux to circuit structures. Depending on moat structure, the coupling from a few moat-captured fluxons is shown to reduce the critical current for a SQUID by 20% or more, which justifies a thorough analysis. We present results for this very important aspect of magnetic rule checking and show how controlled flux trapping experiments in designated moats yield measurement results that fit simulated predictions very well. With the simulation tools validated, we show how flux trapping is incorporated into compact simulation models and we detail the extraction of magnetic coupling and the calculation of the compact models for both branch and loop-type simulations. We also show how phase-based simulation with the circuit simulator JoSIM allows arbitrary fluxon insertion in moats during transient circuit simulation and conclude with some recommended design rules for moat geometry, size, and placement.

Superconductive Circuits and the General-Purpose Electronic Simulator APLAC

Abstract: The general-purpose circuit simulator analysis program for linear active circuits (APLAC) is not widely known within the superconductor circuit community, regardless of its built-in Josephson junction model and capability of modeling the superconductive phase transition with controlled sources We review the use of APLAC to model, eg, noisy dc SQUIDs and transition-edge sensors Based on an APLAC simulation, we also comment on the preference of voltage bias over current bias in dc SQUIDs in applications where large dynamic range and high bandwidth are simultaneously required

Broadband Circuit Model for EMI Analysis of Complex Interconnection Networks in Metallic Enclosures of Arbitrary Shape

Abstract: In this article, a broadband equivalent circuit was developed to model the electromagnetic behavior of complex interconnection structures in metallic casings of arbitrary geometry. Based on the eigenfunctions of the system, this model is inherently stable in the time domain due to its passivity and allows simulation by a commercial circuit simulator with arbitrary linear or nonlinear port terminations. The typically slow convergence of the circuit model is accelerated by the extraction of quasi-static inductances and capacitances and losses are considered by additional resistive elements. The presented model is validated in the frequency domain by elaborate full-wave simulations.

Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework.

Abstract: The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a drift-diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices.

Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits

Abstract: Single-electron transistors (SETs) have been extensively used as charge sensors in many areas, such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal–oxide–semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge the SET signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.

Smartphone Handwritten Circuits Solver Using Augmented Reality and Capsule Deep Networks for Engineering Education

Abstract: Resolving circuit diagrams is a regular part of learning for school and university students from engineering backgrounds. Simulating circuits is usually done manually by creating circuit diagrams on circuit tools, which is a time-consuming and tedious process. We propose an innovative method of simulating circuits from hand-drawn diagrams using smartphones through an image recognition system. This method allows students to use their smartphones to capture images instead of creating circuit diagrams before simulation. Our contribution lies in building a circuit recognition system using a deep learning capsule networks algorithm. The developed system receives an image captured by a smartphone that undergoes preprocessing, region proposal, classification, and node detection to get a Netlist and exports it to a circuit simulator program for simulation. We aim to improve engineering education using smartphones by (1) achieving higher accuracy using less training data with capsule networks and (2) developing a comprehensive system that captures hand-drawn circuit diagrams and produces circuit simulation results. We use 400 samples per class and report an accuracy of 96% for stratified 5-fold cross-validation. Through testing, we identify the optimum distance for taking circuit images to be 10 to 20 cm. Our proposed model can identify components of different scales and rotations.

An Improved Equivalent Circuit Simulation of High Frequency Ultrasound Transducer

Abstract: The equivalent circuit simulation plays an important role in the design of ultrasound transducer. However, the existing methods are difficult to achieve the effect of matching and backing layer, and not able to accurately simulate the transducer with cable. Especially in the application of high frequency ultrasound, the long cable has a great influence on the performance of the transducer. To overcome these limitations, this paper proposed an improved equivalent circuit method, which combined Leach model and transmission line model. It can realize the complete simulation of ultrasound transducer with a long cable, matching layer, and backing layer in PSPICE circuit simulation software when the parameters were measured. Its principles were briefly introduced, and ultrasound transducers with different frequencies (12 and 20 MHz), different matching layers, and different cable lengths (0.5-2.5 M) were designed and fabricated to verify the effectiveness of the method, which is also compared with the traditional KLM method using PiezoCAD. The experiment results showed that the long cable, matching layer, and backing layer have a significant impact on the performance of high frequency ultrasound transducers, and this proposed method has good agreement with these results. Moreover, for the simulation of the complete transducer, the effect of this method is better than KLM model. Besides, this method does not need to know the specific equivalent circuit of matching, backing layer, or cable wire, it can accurately predict the impedance and phase of the transducer through the material parameters, which is very helpful for the material selection and optimization of subsequent transducer design and fabrication. The study indicates that this improved equivalent circuit method is suitable to be applied in the general circuit simulation software and provides strong support for the high frequency transducer and system design.

Machine Learning Regression-Based Single-Event Transient Modeling Method for Circuit-Level Simulation

Abstract: In this article, a novel machine learning regression-based single-event transient (SET) modeling method is proposed. The proposed method can obtain a reasonable and accurate SET model without introducing complex physical mechanisms, which are not suitable for circuit-level simulation, into the model. To capture the essential physics behind these current transients caused by SET in the circuit-level simulations, we collect plenty of SET current data under different conditions [e.g., different linear energy transfer (LET), different drain bias voltage, different strike position, etc.] to train the SET model. To show the effectiveness of the proposed modeling method, we build a SET pulse current model by learning SET current data of Semiconductor Manufacturing International Corporation (SMIC) 130-nm bulk CMOS obtained by TCAD simulation. A multilayer feedforward neural network is used to build the SET pulse current model and the built SET model takes into account the dependence of time, LETs, drain bias voltages, and strike positions. The results from the model are validated with the simulation from TCAD. The trained SET pulse current model is implemented as a Verilog-A current source in the Cadence Specter circuit simulator, and an inverter with five fan-outs is used to show the practicability and reasonableness of the proposed SET pulse current model for circuit-level single-event effect (SEE) simulation.

Revisiting the nodal voltage method for both human comprehension and software implementation: Towards a teaching/self-learning simulation tool

Abstract: This paper outlines an application—dubbed U=RIsolve (read as “you resolve”)—for helping students to learn the Nodal (or Node) Voltage Analysis method (NVM, for short) for electrical circuit analysis. The NVM enables determining the voltage in every Node in the circuit, related to a reference (Ground) Node. In turn, this enables to compute the current in every Branch (and therefore, the voltage across every component). The U = RIsolve application goes far beyond the capabilities of traditional circuit simulators; as it outputs the fundamental circuit information, the methodology, the equations, and the results related to the NVM for a given circuit previously simulated in Quite Universal Circuit Simulator (QUCS). QUCS can generate a text file (called netlist) that identifies all the circuit components/connections and that serves as an input to the U = RIsolve application. Additionally, users can also upload the circuit schematics to facilitate the analysis of the U = RIsolve output. Then, the user just needs to click a button to get all the reasoning of the NVM analysis.

Stim: a fast stabilizer circuit simulator

Abstract: This paper presents ``Stim", a fast simulator for quantum stabilizer circuits. The paper explains how Stim works and compares it to existing tools. With no foreknowledge, Stim can analyze a distance 100 surface code circuit (20 thousand qubits, 8 million gates, 1 million measurements) in 15 seconds and then begin sampling full circuit shots at a rate of 1 kHz. Stim uses a stabilizer tableau representation, similar to Aaronson and Gottesman's CHP simulator, but with three main improvements. First, Stim improves the asymptotic complexity of deterministic measurement from quadratic to linear by tracking the {\em inverse} of the circuit's stabilizer tableau. Second, Stim improves the constant factors of the algorithm by using a cache-friendly data layout and 256 bit wide SIMD instructions. Third, Stim only uses expensive stabilizer tableau simulation to create an initial reference sample. Further samples are collected in bulk by using that sample as a reference for batches of Pauli frames propagating through the circuit.

A MOSFET SPICE Model With Integrated Electro-Thermal Averaged Modeling, Aging, and Lifetime Estimation

Abstract: Lifetime estimation of power semiconductor devices have been widely investigated to improve the reliability and reduce the cost of maintenance of power converters. However in most reported work, the aging effect is not considered in the lifetime evaluation process due to the omission or limitation of thermal cycle counting method. Additionally, the electrical/thermal simulation and lifetime estimation are usually implemented in different simulators/platforms, for the same reason. Thus, to tackle these problems, a concise but comprehensive MOSFET model that enables electro-thermal modeling, aging and lifetime estimation on LTspice® circuit simulator is proposed in this paper. The idea comes from the fact that, MOSFET on-state resistance $R_{ds,on}$ is not only temperature dependent, but also widely accepted as the device failure precursor. In other words, as it carries critical information about instantaneous temperature and aging progress. Hence, co-simulation can be achieved by constructing electrical, thermal, and aging and lifetime sub-modules exclusively first, and using $R_{ds,on}$ , to build linkages among them. Averaged modeling technique is adopted due to the ease of establishing links among these three sub-modules, and fast simulation speed as compared to a switched converter model. Behavioral models are employed to realize the thermal cycles counting, stress accumulation and degradation evaluation. This paper demonstrates that it is possible to use a single simulation software to monitor performances of devices and circuits, and their lifetime estimation simultaneously. High-stress thermal cycling and long-term random mission profiles are applied to verify the correctness of the model and to mimic a 10-year load respectively. An accelerated aging trend can be observed in the long-term mission profile simulation, which is in agreement with the theory. Facilitated by the employment of averaged circuits, the proposed method is a good simulation/analytical tool to implement a long-term mission profile that requires reliability assessment.

A Complete Flow of Miniaturizing Coil Antennas Based on Matching Circuit

Abstract: This paper proposes and verifies a complete design flow of miniaturizing a coil antenna and widening its impedance bandwidth for near-field application, such as NFC, RFID and WPT. The proposed scheme based on mature electronic element matching technology is interpreted in detail by two equivalent circuit models in theory. For convenience, only the series equivalent circuit and its matching circuit are respectively established in the circuit simulator ADS and ANSYS HFSS to assess the scheme proposed from two aspects. The parallel equivalent circuit can be optimized by a similar approach. Then, a WPT system is established in HFSS to further verify the feasibility of miniaturization. Finally, the dimension of the coil antenna can be reduced by about 70%, and its impedance bandwidth can be increased by approximately 40% after two electronic modules are integrated.

Automatic Surrogate Model Generation and Debugging of Analog/Mixed-Signal Designs Via Collaborative Stimulus Generation and Machine Learning

Abstract: In top-down analog and mixed-signal design, a key problem is to ensure that the netlist or physical design does not contain unanticipated behaviors. Mismatches between netlist level circuit descriptions and high level behavioral models need to be captured at all stages of the design process for accuracy of system level simulation as well as fast convergence of the design. To support the above, we present a guided test generation algorithm that explores the input stimulus space and generates new stimuli which are likely to excite differences between the model and its netlist description. Subsequently, a recurrent neural network (RNN) based learning model is used to learn divergent model and netlist behaviors and absorb them into the model to minimize these differences. The process is repeated iteratively and in each iteration, a Bayesian optimization algorithm is used to find optimal RNN hyperparameters to maximize behavior learning. The result is a circuit-accurate behavioral model that is also much faster to simulate than a circuit simulator. In addition, another sub-goal is to perform design bug diagnosis to track the source of observed behavioral anomalies down to individual modules or small levels of circuit detail. An optimization-based diagnosis approach using Volterra learning kernels that is easily integrated into circuit simulators is proposed. Results on representative circuits are presented.

A New Low-cost Hardware-in-the-Loop Simulator for Control of Power Electronics Systems Laboratory

Abstract: Laboratory is very important in engineering education but setting up a laboratory is related in a huge investment. Traditional laboratory also requires students to present at the laboratory. Since 2020, the COVID-19 outbreak prevents students from the onsite studying. The lecture class can be deficiently substitute by online class but the laboratory is heavily impacted and still has no good solution. A virtual laboratory or a low-cost hardware-in-the-loop can reduce the severity of the problem. This paper presents a new hardware-in-the-loop simulator for control of power electronics systems laboratory. The proposed system uses a low-cost analog I/O hardware to link the physical control signal to student’s PC and act as a virtual power electronics circuit simulator. As the PC is not the real-time high-performance simulator, the time-scaling technique is used. The result and discussion have shown that the developed system is very useful in many aspects.

Towards the Co-Simulation of Charge Qubits: A Methodology Grounding on an Equivalent Circuit Representation

Abstract: This paper presents a methodology to describe quantum mechanical states of charge qubits, realized as coupled quantum dots occupied by single electrons, using equivalent electrical circuits. We explain how to construct all equations starting from low-level simulations of wave functions and interpret the relationship between the parameters appearing in the resulting model and the parameters of the physical system. An efficient methodology to obtain 2D wave functions is presented. Results obtained in this study using a circuit simulator correspond to quantum dot arrays fabricated in a CMOS technology and recently published in the literature. The generalization of quantum mechanical equations, their conversion to equivalent circuits, and numerical examples are discussed.

Design of Magnetic Coupling Mechanism with Gentle Excursion Performance for Wireless Power Transfer System

Abstract: While working for wireless charging system mutual inductance coil offset will cause magnetic coupling institutions to drop, causes the output voltage and reduce the transmission power of the problems, the article design a migration resistance excellent electric vehicle wireless power transfer (Wireless Power Transfer, WPT) system, the system adopts the LCC/LCC compensation topology and in the primary side reverse winding coil round asymmetric magnetic coupling structure. This paper describes the coil type and the basic principle of asymmetric structure used in the magnetic coupling mechanism, analyzes the effect of adding the reverse winding coil on the migration performance of the magnetic coupling mechanism, and gives the design method. Finally, circuit simulation software is used to simulate the system. The results show that when the transmission distance is 150mm and the horizontal deviation reaches 100mm, the system can still output constant power.

Novel Offline Software-in-the-Loop Simulation Technique for Modular Single-Phase Flyback Current Source Grid-Tie Inverter System

Abstract: This paper proposes a novel approach in the offline Software-in-the-Loop (SIL) simulation technique to speed up the firmware development cycle of power electronics and enhance the firmware maintenance of commercial products. In the conventional SIL simulation process, Model-in-the-Loop (MIL) is always performed prior to the execution of SIL because it allows users to automatically generate C code for testing in the subsequent SIL. Furthermore, the target device can be programmed with the compiled files only if the simulation tools support specific models of control chips. In light of this, the goal to use SIL to validate firmware in early power electronics product development becomes more complex and limited due to the limited selection of simulation tools. In this paper, non-preemptive scheduling (NPS) and common firmware architecture (CFA) are explored to illustrate the integration of the application layer for implementing the proposed offline SIL. Users can directly use circuit simulation software that supports Dynamic-Link Library (DLL) to simultaneously develop source codes and verify the offline SIL process of the product. To further illustrate the practical application of the power electronics product in the microcontroller (MCU) mock model and the power stage circuit model, a single 300W power module composed of three single-phase quasi-resonant (QR) flyback current source converters connected in parallel and cascaded with an H-bridge unfolder is used as an example to execute offline SIL in the SIMULINK. Finally, a system-level experiment was conducted to validate the firmware of 16 power modules assembled in a 4.8 kW fuel cell (FC) grid-tie inverter system, which was modulated through the power management unit (PMU) and the monitoring graphical user interface (GUI).

Improved Modeling of a Multi-Level Inverter for TACS to Reduce Computational Time and Improve Accuracy

Abstract: A modeling of a turbo air compressor system (TACS), with a multi-level inverter for driving variable speed, combining an electrical model of an electric motor drive system (EMDS) and a mechanical model of a turbo air compressor, is essential to accurately analyze dynamics characteristics. Compared to the mechanical model, the electrical model has a short sampling time due to the high frequency switching operation of the numerous power semiconductors inside the multi-level inverter. This causes the problem of increased computational time for dynamic characteristics analysis of TACS. To solve this problem, the conventional model of the multi-level inverter has been proposed to simplify the switching operation of the power semiconductors, however it has low accuracy because it does not consider pulse width modulation (PWM) operation. Therefore, this paper proposes an improved modeling of the multi-level inverter for TACS to reduce computational time and improve the accuracy of electrical and mechanical responses. In order to verify the reduced computational time of the proposed model, the conventional model using the simplified model is compared and analyzed using an electronic circuit simulation software PSIM. Then, the improved accuracy of the proposed model is verified by comparison with the experimental results.

CMOS Mixed-Signal Spiking Neural Network Circuit Using a Time-Domain Digital-To-Analog Converter

Abstract: This paper proposes a high energy efficiency CMOS mixed-signal spiking neural network circuit using a time-domain digital-to-analog converter (TDAC) for realizing online and on-chip brainmorphic learning hardware. The circuit consists of a mixed-signal synapse circuit and an analog leaky integrate-and-fire neuron circuit. The TDAC converts synaptic weights held by digital memory into an analog current that realizes a biologically plausible synaptic response, which is employed as an output stage for our synapse circuit. To evaluate online and on-chip learning operation, the remote supervised method (ReSuMe) was implemented using TSMC 40-nm (1-poly, 8-metal) CMOS technology, and this circuit was evaluated by a Spectre circuit simulator. The circuit simulation results show that energy per synaptic event in our circuit was 20.1 fJ for multiply-accumulation operation and 92.1 fJ for ReSuMe.

Assessment of 2D-FET Based Digital and Analog Circuits on Paper

Abstract: Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view of their attractive electrical and mechanical properties. This work investigates molybdenum disulfide (MoS2) based field-effect transistors (FETs) fabricated on paper substrate for designing both digital and analog circuits, such as inverter, current mirror, and Physical Unclonable Function (PUF) bitcell. Electrical measurements of fabricated devices are exploited to setup a look-up-table (LUT)-based Verilog-A model to be integrated in a commercial circuit simulator. Obtained results prove the potential of paper-based MoS2 FETs as building blocks of next-generation integrated circuits for a wide range of practical applications.

Synthesis of a Cauer Equivalent Circuit for Electric Devices From Computed and Measured Data

Abstract: This article proposes a method for modeling electric devices based on a Cauer circuit whose circuit parameters are directly determined from measured or computed data using the adjoint variable method. It has been shown that electric devices that are governed by the quasi-static Maxwell's equation can be modeled by the Cauer circuit. From the synthesized Cauer circuit, eddy current losses can be evaluated for a wide frequency range. Moreover, it can be embedded into a circuit simulator to perform the time-domain analysis. It is shown that the Cauer circuit whose parameters are identified using the proposed method works better for a simple numerical model than that whose parameters are identified using a genetic algorithm. Moreover, the Cauer equivalent circuit of a reactor and a power inductor is synthesized from the measured data using the proposed method. It is shown that the input impedance of the reactor and power inductor is well approximated by the Cauer circuit over the frequency domain of interest.

Cut-Off Frequency Analysis of Ridged Rectangular Waveguide Based on Its Equivalent Circuit

Abstract: This paper presents an analysis of cut-off frequency for a ridged rectangular waveguide based on its equivalent circuit. The conventional rectangular waveguide is employed as the initial configuration to determine the equivalent circuit which consists of capacitors and inductors. Values of both components are deriving by the cut-off frequency and source impedance. Here, a double-ridged rectangular waveguide is utilized to represent a ridged waveguide whereby its cut-off frequency is applied as a key parameter in the analysis. The proposed equivalent circuit was validated by comparing the cut-off frequency obtained from theoretical approach and EM & Circuit simulator software for several frequency bands. In addition, variation of space between ridges has also confirmed the validity of the proposed equivalent circuit. As a further investigation, the dielectric material loading into the conventional rectangular waveguide and the dielectric material insertion between the ridges are provided to demonstrate the performance of proposed equivalent circuit in lowering the cut-off frequency.

Strengthening the Practical Capacity of Students: an Educational Case Study about Teaching Feedback in Electronics Circuit

Abstract: Facing the requirements of advancing the strategy of training elite talents, optimizing the talent training system and building first-class undergraduate education, the training of elite talents not only emphasizes problem – solvingl “how to do it?”, but also emphasizes thinking about problemsl “what to do?” to help students view and solve problems from a broader perspective, interdisciplinary and systematic thinking. In the teaching process of “electronic circuits”, we have clearly realized that with the rapid development of electronic circuit technology, electronic equipment has become increasingly integrated, electronic design automation (EDA) and the rapid development of various circuit simulation software have greatly simplified the complex circuit analysis and calculations. Because the world is analog, the signals in nature are analog signals, and analog circuits are inseparable from real life. Therefore, we have proposed a comparative teaching strategy of electronic circuit technology with “analogous thinking method”. The so-called analogy thinking refers to the logical reasoning method that transfers the knowledge of one special thing to another special thing based on the similarity or similarity in some aspects between two or two kinds of things. When two types of things are the same or similar in one or some aspects, analogy thinking can be used. In this paper, application of analogy as well as inspiring methodology in teaching feedback amplifier circuit have been given as a case study.