Showing papers on "Electronic design automation published in 1982"

Timing analysis of computer hardware

Abstract: Timing Analysis is a design automation program that assists computer design engineers in locating problem timing in a clocked, sequential machine. The program is effective for large machines because, in part, the running time is proportional to the number of circuits. This is in contrast to alternative techniques such as delay simulation, which requires large numbers of test patterns, and path tracing, which requires tracing of all paths. The output of Timing Analysis includes "Slack" at each block to provide a measure of the severity of any timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach. This system has successfully detected all but a few timing problems for the IBM 3081 Processor Unit (consisting of almost 800 000 circuits) prior to the hardware debugging of timing. The 3081 is characterized by a tight statistical timing design.

MEDUSA--A Simulator for Modular Circuits

Abstract: A modular circuit is defined as a combination of a certain number of k-modules, which are embedded in a carrier network The modules may represent subcircuits of varying complexity down to single devices Such modular circuits lend themselves to a description by a system of modular equations MEDUSA is a user-oriented simulator which utilizes system modularity during the simulation process itself, ie, for solving the underlying equations This approach enables the consistent numerical solution of both the basic equations of several bipolar devices and the network equations for a circuit environment Hence, MEDUSA in its present state is a merged device-circuit simulator meeting simultaneously the requirements of device and circuit design

Automated Synthesis of Digital Hardware

Abstract: This paper describes a portion of the Carnegie-Mellon University Design Automation (CMU-DA) research. This part involves the design and construction of a data-memory allocator, consisting of a set of algorithms and data structures which synthesize hardware at the register-transfer level from a behavioral description written in ISP. The allocator selects registers and data operators and interconnects them with data paths to form a data part capable of implementing the data operations specified in the behavior. Results indicate that the allocator's performance compares favorably with a human designer when designing an elevator controller and a reduced PDP-8/E. Although optimal designs cannot be guaranteed, upper bounds for the number of components used can be derived from the ISP description.

A Database Approach for Managing VLSI Design Data

Abstract: We describe an approach to managing information about VLSI designs, founded upon database system methods. A database component provides a low-level flat-file interface to stored data. Built on top is a design data management system, supporting the hierarchical construction of a design from primitive cells, and organizing data about alternative design representations and versions. Programs to provide a tailored interface to design data are also provided. The system simplifies the rapid construction of new design tools by taking responsibility for design data management.

Intersystem Data Transfer Via IGES

Abstract: The IGES standard addresses CAD/CAM data-exchange problems the industry faces today. End users as well as developers will be responsible for its success or failure.

CAD Systems for IC Design

Abstract: As integrated circuit (IC) complexities increase, many existing computer-aided design (CAD) methods must be replaced with an integrated design system to support very large scale integrated (VLSI) circuit and system design. The framework for a hierarchical CAD system is described. The system supports both functional and physical design from initial specification and system synthesis to simulation, mask layout, verification, and documentation. The system is being implemented in phases on a DECSystem 20 computer network and will support evolutionary changes as new technologies are developed and design strategies defined.

A Symbolic Design System for Integrated Circuits

Abstract: As integrated circuit design has become increasingly complex, the need for more effective data description techniques has become critical. Design verification from mask artwork data alone can consume vaste amounts of computer time for VLSI circuits, if it can be performed at all. The use of a symbolic design description, which allows the designer or synthesis program to express circuit structure as well as maintain full connectivity information, can reduce dramatically the burden placed on the verification tools. This paper describes a symbolic design system, its associated data manager, its color graphics viewport manager, and its application to a variety of design methods. The data manager can store a variety of representations of the design, including simulation data, geometric layout, symbolic layout, and schematic diagrams. The viewport manager can manage a number of viewports concurrently and the use of a model frame buffer allows it to function easily on a variety of graphics terminals and hard-copy devices. The system is designed with an engineering work station in mind.

Hierarchical Top-Down Layout Design Method for VLSI Chip

Abstract: A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.

Electronic Design Automation

Abstract: Resources You are free to use any books, articles, notes, or papers as references. Provide citations in your writeup as appropriate. Writeup Writeup should be in an electronically readable format (HTML or PDF preferred). Energy Model For this assignment we'll use a simple energy model. We lump all ca-pacitance for the nodes to the LUT input and assume this is the same for all LUTs (so this ignores effects of wire lengths, just as the unit delay assumption does). We assume the dominant energy is the energy taken to switch each of these inputs. The energy is thus: E circuit ∝ all gate inputs (P switch (input)) For covering, assume the input netlist is already annotated with the switching probability of each gate. Particularly, gate inputs in the input netlist which are hidden inside a mapped gate during covering do not contribute to the energy for the mapped circuit. Problems 1. In class, we have assumed our target netlists have multiple outputs. If our function only has a single output, does that simplify any of the problems we have been addressing? (e.g. does optimal covering for area still remaining NP-hard? or can we exploit this restriction to get an optimal solution in reasonable time?) Explain why or why not. 2. Show an example where all three optimization criteria would give rise to different optimal coverings: • area (in LUTs) • delay (in LUT delays; you may assume fanout does not affect delay)

Cellular Image Processing Techniques for VLSI Circuit Layout Validation and Routing

Abstract: The architecture of the Cytocomputer?, an existing special-purpose, pipelined cellular image processor, is described. A formalism used to express cellular operations on images is then given. Cellular image processing algorithms are then developed that perform (1) design rule checks (DRC's) on VLSI circuit layouts, and (2) Lee-type wire routing. Two sets of cellular image processing transformations for checking the Mead and Conway design rules and for Lee-routing have been defined and used to program the Cytocomputer. Some experimental results are shown for these cellular implementations.

Modular Description/Simulation/Synthesis using DDL

Abstract: With the increased complexity of integrated circuits, a true top-down methodology is mandatory in their design. A construct that enables a modular description of a system design is added to DDL. The Translator, Simulator and Synthesis Software has been modified to retain this modularity throughout the design cycle. These enhancements allow a multi-level simulation and multi-technology synthesis of an integrated circuit.

Designing Gate Arrays Using a Silicon Compiler

Abstract: This paper describes a programming environment in which gate array designs can be developed. It allows the engineer to design for performance, wirability and testability by manipulating a textual description of a design. The principle features of this are a high-level language for design description, completely automatic layout, and an integrated simulator. The total package can be referred to as a silicon compiler in the gate array design style.

Designer's Workbench: Delivery of CAD Tools

Abstract: Designer's Workbench (DWB) is a systematic approach to design aids integration that overcomes most of the barriers that frequently restrict the use of those aids. In combination with the UNIX (FOOTNOTE: UNIX is a trademark of Bell Laboratories.) operating system [1][2], DWB manages both the flow and the form of data that is required by application programs that reside on various computer systems. The techniques described in this paper enable the Designer's Workbench development team to respond quickly to electrical and physical designers' needs. Because of this ability to respond quickly to users' needs Designer's Workbench has had uncommon growth and acceptance in the user community.

A Design Methodology based upon Symbolic Layout and Integrated CAD Tools

Abstract: This paper describes one of the new methodologies for IC design currently being used at the CNET. The main features detailed are the symbolic layout method called MDMOS and the integrated CAD system CASSIOPEE. Its most significant advantages are design safety, elimination of costly and inefficient checks and supply of technical specifications which are always up-to-date. This methodology is described in its entirety starting from the logical description, and including all stages up to masks generation.

A highly automated semi-custom approach for VLSI

Abstract: The structured approach is aimed at optimizing the chip physical design while keeping design resources and time at a reasonable level. The logic is partitioned into data flow logic and control logic; a specialized physical structure has been defined to match the data flow logic structure and the gate array has been chosen for control logic implementation, both physical structures being customizable. A general purpose library and a set of design automation programs have been developed to allow fast physical design of the functional partitions according to the applications. A bipolar 16-bit slice microprocessor has been designed with this approach and built; compared to the widely used gate array chip implementation, it shows an improvement of 2 in gate density and 1.5 in power dissipation. The physical design of this 2000 gates chip took only two months.

Automation in semiconductor manufacturing

Abstract: Some backgrounds and trends of semiconductor technology will be reviewed in conjunction with production automation. Experiences are presented for the case of the advanced MOS wafer processing area, including the basic philosophy and equipment implementation. History of the automation in assembling area will follow including some existing examples. Semiconductor technology keeps changing towards smaller dimension, larger die size, larger number of pins, and larger number of product types. One of the big problems lies in the fact that the throughput of equipments is getting lower as the geometry getting finer, and major breakthrough is expected. Future opportunities and related problems will be discussed.

An Interactive Logic Synthesis System Based upon AI Techniques

Abstract: This paper proposes an interactive logic synthesis system which supports translation from behavioral to gate level. A design's specification described in the register transfer language DDL is translated into abstract objects. They are converted to macros representing logical structure and serving as technology independent goals which guide designers in synthesis phases. The system has knowledge about the technology adopted and can accommodate various know-how and design constraints to support the designer's tasks of PCB partition and logic synthesis. As a result, it greatly relieves designers from tedious tasks and makes it possible to explore alternative designs.

Application of singular pencil representations to control system design

Abstract: Three properties of a singular-pencil model of linear systems are reviewed to show its feasibility as a data structure for computer-aided design. The direct relationship of the representation to implicit nonlinear models is demonstrated. Algebraic topics including minimality and canonicity are summarized, and then a frequencydomain design example is used to illustrate the application of an existing command language for system manipulation. Algebraic design methods are discussed briefly, and a design example illustrating a new method for stable factorization is illustrated. Optimization and identification are shown to be feasible using pencil models. Finally extensions to multidimensional systems will be discussed.

Evolution of the Engineering Design System Data Base

Abstract: The IBM Engineering Design System is a corporate-wide electronic design automation system used for the development of the 3081 and other machines incorporating LSI chips and their carriers. Initially planned in the late 1960s, the system has evolved to respond to a changing set of requirements. This paper describes the evolution of the system data base, as well as the steps taken to ensure the integrity of the data and the correctness of the design.

A bit map architecture and algorithms for design automation

Abstract: An architecture is presented for improving the run-time performance of integrated circuit design automation programs by efficiently manipulating bit data structures: one and two dimensional boolean arrays. Contrary to other approaches where a specific algorithm is constructed in hardware, this architecture provides a simple instruction set allowing a variety of algorithms to be implemented. The proposed machine architecture is a single instruction multiple data stream machine. One-bit processors are connected in a rectangular matrix where each processor can communicate directly with its four orthogonal neighbors. Two similar designs are considered: first, a processor is dedicated to each data point, requiring a large number of processors for realistic size problems; in the second architecture, each processor manipulates many data points which reduces the processing power but simplifies the hardware requirements. In the second design, the architecture can manipulate arrays much larger than the number of physical processors. Integrated circuit mask verification (design rule checking), a maze router (Lee's algorithm), an electrical field solution, and boolean equation manipulation (bit vectors) are used as examples of design automation problems that benefit from the proposed architecture. Using an architectural simulator, performance estimates indicate run-time improvements of several orders of magnitude over sequential computer solutions. To prove the processor design, a single cell was implemented as an NMOS integrated circuit.

A Design System Approach to Data Integrity

Abstract: Due to the nature of chip design, the Very Large-Scale Integrated (VLSI) design data base is constantly changing. The changes may be caused by logical or physical design activities. In either case, there is a need to make sure that no matter what happens, the data base remains valid. This paper discusses a system which uses an Automated Data Integrity Technique (AUDIT) to eliminate errors prior to hardware build.

A Retrospective on Software Engineering in Design Automation

Abstract: We have observed the effect that software engineering can have on design automation throughout the four years of the Designer's Workbench (DWB) project. DWB is a design aids delivery system that interfaces the user to a variety of applications programs. This paper describes our experience in using various techniques and our conclusions about their value. The improvements that occurred in the second design iteration illustrate the effect of using a consistent methodology. The introduction of table-driven, finite state machines and software utilities provided an unusually adaptable and flexible environment for adding new applications. The resultant design aids delivery system is able to respond to the rapid changes that occur in the supported technologies and provide tools when needed rather than after the customers have completed their project.

Automated Conversion of Design Data for Building the IBM 3081

Abstract: The Manufacturing Release Processing System for handling the dual design methodology employed by IBM in the design of the 3081 is described in this paper. This methodology consists of (Part 1) the design of basic building blocks, such as standard circuits and structured gate arrays, on which these standard circuits can be placed and interconnected during (Part 2), when numerous unique devices are designed to perform the various logical functions within the processor. This dual design methodology created some difficult challenges to IBM's CAD/CAM system designers. This paper focuses on the automated release process and how it meets the specific challenges of processing large volumes of design data in the minimum time demanded by fast, controlled implementation of engineering changes.

Measurements of a VLSI Design

Abstract: This paper presents data about three facets of a recently-completed VLSI design containing 45000 transistors. The first set of data describes the mask-level features of the circuit, from which it is seen that almost all features have at least one small dimension. The second set of data analyzes the hierarchical cell structure used by the designers to specify the circuit. The measurements show that composite cells have a different structure from primitive cells, and that, outside of arrays, cells are rarely re-used. The third set of data concerns the usage of an interactive layout program during the circuit's design. In spite of the circuit's size, the most frequently invoked commands were all simple.

LAMBDA: A quick, low cost layout design system for master-slice LSI s

Abstract: This paper describes an automatic/interactive layout design system for designing master-slice LSI chips, which places function blocks and gives wiring patterns on the chip. Since 100% routing is essential for master-slice layout design, it is urgently required to establish a strong CAD system, which significantly reduces the design time. The LAMBDA system has been developed to achieve complete net connectivity in as short a design time as possible, where efficient automatic procedures are implemented as well as highly interactive functions. The system adopts two-level hierarchy algorithms for placement and routing problems. Highly interactive functions are realized by exploiting human intelligence and the computer's high speed processing.

Defining and Implementing a Multilevel Design Representation with Simulation Applications

Abstract: A design representation that incorporates descriptions at more than one level of abstraction is called a multilevel representation. This paper describes a multilevel representation which includes behavioral and structural levels of description, and a multilevel analysis aid, called timing abstraction, which extracts timing information from a structural design and adds it to a behavior level description. With this design aid, alternate implementations of the same behavior, generated using the CMU-DA synthesis software, can be compared using a behavior level simulator. The timing accuracy is that of the microcode impleinentation, while the speed of the simulation is that of a behavior level simulator.

ICAD/PCB: Integrated Computer Aided Design System for Printed Circuit Boards

Abstract: The advanced computer aided design system, ICAD/PCB, was recently put into operation at Fujitsu. The system provides designers with powerful tools to significantly lower the cost and the time required to design and manufacture printed circuit boards (PCBs). Interactive and automatic facilities to support the entire PCB design process are integrated in the ICAD/PCB system.

An Interactive Simulation System for Structured Logic Design -- ISS

Abstract: An Interactive Simulation System (ISS) is presented. ISS is an integrated interactive CAD system for logic design, and is configurated "module oriented" to support structured logic design. An Interactive Simulator (IS) is used for design verification. A designer can control simulation steps interactively in IS, and he can find design errors early using a good interactive interface. A Structured Hardware Design Language (SHDL) is used to describe logic designs.