Showing papers on "Electronic design automation published in 1986"

Automated Synthesis of Data Paths in Digital Systems

Abstract: This paper presents a unifying procedure, called Facet, for the automated synthesis of data paths at the register-transfer level. The procedure minimizes the number of storage elements, data operators, and interconnection units. A design generator named Emerald, based on Facet, was developed and implemented to facilitate extensive experiments with the methodology. The input to the design generator is a behavioral description which is viewed as a code sequence. Emerald provides mechanisms for interactively manipulating the code sequence. Different forms of the code sequence are mapped into data paths of different cost and speed. Data paths for the behavioral descriptions of the AM2910, the AM2901, and the IBM System/370 were produced and analyzed. Designs for the AM2910 and the AM2901 are compared with commercial designs. Overall, the total number of gates required for Emerald's designs is about 15 percent more than the commercial designs. The design space spanned by the behavioral specification of the AM2901 is extensively explored.

Cathedral-II: A Silicon Compiler for Digital Signal Processing

Abstract: The article describes the status of work at IMEC on the Cathedral-II silicon compiler. The compiler was developed to synthesize synchronous multiprocessor system chips for digital signal processing. It is a continuation of work on the Cathedral-I operational silicon compiler for bit-serial digital filters. Cathedral-II is based on a ?meet in the middle? design method that encourages a total separation between system design and reusable silicon design. The CAD system includes a rule-based synthesis program, a procedural program, and a controller synthesis environment. Processors are synthesized in terms of modules called from automated reusable module generators. Chip layout is done on a floor planner. An expert subsystem verifies correctness during silicon design and generates functional and timing models for verification at the module and chip levels.

SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic

Abstract: This paper presents SOCRATES, a system of programs which synthesize and optimize combinational logic circuits from boolean equations. SOCRATES optimizes logic using boolean and algebraic minimization techniques, and it optimizes circuits derived from this logic in a user defined technology with a rule based expert system. This paper discusses the goals of logic synthesis and the capabilities needed in a tool to meet these goals. SOCRATES's capabilities are then presented and demonstrated with experiments run on circuits from the 1986 Design Automation Conference synthesis benchmark set.

Mason: A Global Floorplanning Approach for VLSI Design

Abstract: A global floorplanning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based on a combined mincut and slicing paradigm, in an effort to ensure routability. A slicing-tree representation is employed, upon which efficient traversal operations are applied resulting in area-efficient floorplans. The method allows modules to be specified as having a number of possible dimensions, and considers I/O pads as well as layout constraints. As a global improvement over previous floorplanning efforts, an in-place partitioning scheme is applied in conjunction with a combined exhaustive and heuristic bipartitioning approach. Moreover, a global channel routing and module I/O pin assignment scheme is used for floorplan evaluation, whereby module dimensions are chosen in conjunction with routing area, ensuring compact floorplans. A computer program, Mason, is presented which efficiently implements the approach and provides an interactive environment for designers to perform floorplanning. The performance of the program is discussed in terms of several industrial examples.

Macromodeling and Optimization of Digital MOS VLSI Circuits

Abstract: Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based on device equations, and encapsulate logic gate behavior in a set of simple yet accurate formulas. The optimization algorithm exploits properties of the digital MOS domain to convert the primal optimization problem into a dual form which is much easier to solve. The result is a pair of CAD tools that can optimize a circuit in roughly the amount of time needed to perform a transistor-level simulation of the circuit.

Synthesis and Optimization of Multilevel Logic under Timing Constraints

Abstract: The automation of the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry, and guarantee functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on the logic. This paper describes SOCRATES, a synthesis system capable of generating combinational logic in a given technology under user-defined timing constraints. We believe this system is the first to perform optimized, delay-constrained, multilevel synthesis into standard cell libraries. Applied to a large number of examples, the system has successfully traded off area versus delay and performs optimized, delay-constrained, multilevel synthesis into standard cell libraries.

A Design Utility Manager: the ADAM Planning Engine

Abstract: In this paper we present a software package which manages the digital design process using a planning paradigm. Under this paradigm design is seen as a process in which abstract models of operators are applied to abstract models of design states in a simulated or planning space, until a sequence of operators has been constructed to completion. The hypothetical design represented by the terminal state is then estimated. Either the planning is then repeated, or the sequence, or plan, is then executed, or carried out, in an execution space. This execution is monitored for violation of expectations; if violations occur, control is returned to the planner. The knowledge base of the planner is populated with register transfer level (RTL) concepts, and it can be populated with other knowledge sets. The planner forms part of the USC ADAM (Advanced Design AutoMation) system.

CINNAMON: Coupled Integration and Nodal Analysis of MOS Networks

Abstract: The use of simulation tools to verify the behavior of integrated circuits is a well established technique for circuit design. This paper describes a novel approach for circuit simulation that promises a significant improvement over conventional methods. The algorithm involves an explicit event driven technique that seems stable even when the accuracy of the solution is relaxed, and is able to perform automatic and dynamic partitioning of the network, thus allowing the full exploitation of latency in large digital networks. Although the basic method could be generalized for any type of circuit, in this paper the scope is limited to MOS integrated circuits.

VLSI CAD Tool Integration Using the Ulysses Environment

Abstract: Ulysses is a VLSI CAD environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. An example of an integrated circuit layout design task is provided. The use of Ulysses in performing this task is discussed in detail.

Statistical Integrated Circuit Design and Characterization

Abstract: A system for the parametric statistical characterization and design of integrated circuits (IC's) is presented. This system integrates many common CAD tools with in-house developed software, and is modular such that old tools can eventually be discarded and new ones installed without disruption. The system supports traditional Monte Carlo, as well as, approximate statistical methods, and spans the entire process, device, and circuit design spaces. Applications are included that demonstrate the many diverse ways the system has been exercised on real-world problems.

An Automatic DFT System for the Silc Silicon Compiler

Abstract: This article discusses design for testability automation for the Silc silicon compiler under development at GTE Laboratories, Inc. Our modular design for testability uses both built-in self-test and scan-path techniques for Slic's full custom VLSI designs. A test controller coordinates the testing of the chip's modules. Testability evaluation is performed using controllability/observability methods, and using a method based on information theory. A testable-by-construction approach is followed in order to synthesize blocks of testable logic. A testability ?expert? manages testability knowledge during the synthesis process and makes the ultimate testability decisions.

Integrating an Electron-Beam System into VLSI Fault Diagnosis

Abstract: Using design data, the system can prepare a logic-state map for the device under test. The map draws top-layer connections in different colors according to their expected logic states so the map may be compared to the DUT image observed by the electron-beam tester. The system has successfully tested a 75K-transistor VLSI device.

SLS - A Fast Switch Level Simulator for Verification and Fault Coverage Analysis

Abstract: We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.

A Statistical Design Rule Developer

Abstract: In this paper, a general methodology for design rule development and the CAD tool which implements this methodology, Statistical Design Rule Developer (STRUDEL), are presented. The focus of the proposed approach is the concept of a statistical design rule, which is defined as a geometric design rule with an associated probability of failure. Global lateral variations obtained from FABRICS, and local spot defects obtained from measurements are taken into account when calculating the probability of failure. A failure model which accounts for catastrophic faults has been enhanced to include some parametric faults. STRUDEL can be used as a guide to generate layout design rules and may be extended to a wide range of applications including coarse yield estimation during design rules check.

Logic Synthesis and Optimization Benchmarks for the 1986 Design Automation Conference

Abstract: In order to compare logic synthesis and optimization systems, a set of benchmarks has been submitted to a number of authors. The results obtained are reported in the present proceedings. This short paper introduces the benchmarks as well as a set of criteria to measure the quality of logic synthesis systems.

Block-Oriented Systems Simulator (BOSS)

Abstract: The Block-Oriented Systems Simulator (BOSS) may be viewed as an operating system that provides a complete interactive environment for simulation-based analysis and design of communication systems. The integrated environment includes the capability to design models, subsystems and systems in a hierarchical fashion using block diagrams, configure and execute a simulation, review the results of the simulation, and perform design iterations. Each of these capabilities is controlled through a consistent user interface using interactive graphics. Recent advances in software engineering, workstation technology, CAD/CAM techniques and expert systems are incorporated in BOSS to provide an intelligent, user friendly and flexible state-of-the-art simulation environment.

A Logic Verifier Based on Boolean Comparison

Abstract: This paper proposes a logic VERIFIER, which verifies the correctness of the gate-level design by comparing it with the behavioral description. An improved Boolean comparison technique, which assures the absence of errors without designer's assist, is proposed. The partitioning and the minimization techniques are effective to reduce the storage required, and indispensable to verify practical sized circuits. If the design is judged incorrect, the system analyzes the result and show the area containing errors. Experimental results have proved that the VERIFIER can detect design errors completely, and indicate them to the designers in comprehensible form.

Hardware Design Languages for Computer Design and Test

Abstract: A standard design and description language will result in a very rich tool base, increased ability to communicate design data, and improved productivity.

VHDL Motivation

Abstract: The goals of the very high speed integrated circuit (or VHSIC) program are to reduce IC design time and effectively insert VHSIC technology into military systems. These goals, indicating the need for a standard means of communication to stream-line advanced digital design and documentation, motivated the development of a hardware description language. Requirements were analyzed during 1981; program organization was formulated during 1982; and the VHSIC hardware description language (or VHDL) program was launched in August, 1983. Acting as a standard design automation interface, VHDL will simplify complex digital system design. Acting as design documentation agent, it will facilitate design insertion into electronic systems. Organization of the VHDL program is detailed elsewhere.1 We will discuss elements motivating hardware description language use (VHDL in particular) and examine its impact on governmental, industrial, and academic participation in electronic research, business, and education.

Design of VLSI Systems

Abstract: VLSI chips have become an important part in the design of many large electronic systems. The growing complexity of VLSI chips creates a need for improved design methodologies and more powerful CAD environments.

A Tutorial Introduction to the Electronic Design Interchange Format

Abstract: The Electronic Design Interchange Format (EDIF) is a neutral data format, through which electronic design information can be exchanged between CAD/CAE systems, semiconductor foundries, fabrication and assembly facilities, etc. The EDIF standard has been under development since November 1983. This paper discusses the history of its development, the organization which supports it, the goals and guidelines followed by the professionals who are developing the standard, and numerous details of the standard itself. Also, an analysis of how well the standard currently covers today's electronic design information is presented, as well as a methodology for developing translators which read and write the format.

A Database Interface for an Integrated CAD System

Abstract: In this paper, an integrated CAD system built around the database COSMIC is briefly introduced, then the COSMIC interface is described in some details. COSMIC is a multi-user, multi-base system, able to take into account multi-level circuit representations, such as functional, logical, symbolic or layout descriptions, as well as connectivity notions at both logical and geometric levels. It also includes protection and security facilities, management of propagation of changes through the design, and mechanisms of communication between databases that allow a team of designers to work in parallel on the same circuit.

Introduction to Semi-Custom Integrated Circuits

Abstract: Several manufacturers have in stock processed silicon wafers for analog and digital circuits which can be customized by one or more layers of metallization to interconnect devices to produce application specific I.C.'s (ASIC). The new CAE/CAD tools make it easy to design functional circuits and run full timing and performance simulation before committing to hardware. ASIC's are cost effective for just one particle physics detector.

PEARL: An Expert System for Power Supply Layout

Abstract: The use of artificial intelligence (AI) expert systems technology has demonstrated its advantages with many new tools in the computer aided design (CAD) field. This paper describes how domain specific knowledge was integrated with a conventional CAD architecture to develop an expert system. The combination resulted in a tool that provides intelligent assistance to printed wiring board (PWB) layout designers. This CAD tool focuses entirely on the layout requirements of power supply circuits for PWBs. The system is called PEARL for Power-supply Expert Assisted Rule-based Layout. PEARL acts as an advisor to the layout designer, providing expert assistance with the placement of components on PWBs. It is presently being enhanced to provide etch routing assistance as well.

Software of silicon? the designer's option

Abstract: Traditionally, the bulk of computer system functionality is implemented in the software medium, as a sequence of instructions for a general-purpose processor. Historically, this has provided the best balance of flexibility, cost, and performance. The new economics of VLSI and continuing advances in VLSI CAD capability open the possibility of application-specific functionality embedded in silicon as a matter of routine. This paper presents several case studies of silicon solutions used in typical software areas, including regular language recognition, Ada program unit replacement, dictionary machines, and string pattern matching. Either software or hardware designers may benefit from a study of such architectures, and Organick's notion of heterosystems designers proficient in both domains is supported.

A frame-based system for the design of electromagnetic devices

Abstract: Developments in computer based analysis systems for magnetic devices have provided the designer with extremely powerful tools for achieving an optimal design. However, the tools have done little to simplify the design task. The introduction of 'expert systems' in the role of design. advisers' can help in the more efficient application of complex analysis systems and thus cut development time. This paper describes the structure of such a system.