Showing papers on "Electronic design automation published in 1991"

Symbolic Analysis for Automated Design of Analog Integrated Circuits

Abstract: 1. Introduction to Analog Design Automation.- 1.1. Introduction.- 1.2. Definitions in analog design automation.- 1.3. Characteristics of analog design.- 1.4. Needs for analog circuits and analog design automation.- 1.5. Different analog design approaches and analog silicon compilation.- 1.6. Analog system-level synthesis.- 1.7. Outline of the book.- 2. The Automated Design of Analog Functional Modules.- 2.1. Introduction.- 2.2. Classification of analog module design programs.- 2.3. An automated design methodology for analog modules.- 2.4. The methodology applied to a simple example.- 2.5. Discussion of and comparison with other analog design systems.- 2.6. Conclusions.- 3. Symbolic Simulation of Analog Integrated Circuits.- 3.1. Introduction.- 3.2. Definition and scope of symbolic simulation.- 3.3. Applications of symbolic analysis in analog design.- 3.4. General description of the ISAAC program.- 3.5. Conclusions.- 4. Algorithmic Aspects of Linear Symbolic Simulation.- 4.1. Introduction.- 4.2. Overview of symbolic analysis techniques.- 4.3. The set-up of the linear circuit equations.- 4.4. The symbolic solution of sets of linear equations.- 4.5. Symbolic expression approximation.- 4.6. Performance of the ISAAC program.- 4.7. Conclusions.- 5. Symbolic Distortion Analysis.- 5.1. Introduction.- 5.2. Symbolic noise analysis.- 5.3. Symbolic analysis of harmonic distortion in weakly nonlinear analog circuits.- 5.4. Symbolic sensitivity analysis and zero/pole extraction.- 5.5. Techniques for the hierarchical symbolic analysis of large circuits.- 5.6. Conclusions.- 6. Analog Design Optimization Based on Analytic Models.- 6.1. Introduction.- 6.2. Circuit sizing based on an optimization of analytic models.- 6.3. The analog design formulation in OPTIMAN.- 6.4. Practical design examples.- 6.5. Automated layout generation of analog integrated circuits.- 6.6. Conclusions.- Appendix A. Characterization of a CMOS Two-Stage OPAMP.- References.

An integrated CAD system for algorithm-specific IC design

Abstract: LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout, and, with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high-sample-rate applications. A number of algorithm-specific ICs designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip are described. >

The interdependence between delay-optimization of synthesized networks and testing

Abstract: As CAD tools become more sophisticated, they can synthesize logic networks that more nearly optimize the circuit area resources to maximize operating speeds. In this work we show, through formal arguments, that the path delays in such optimized networks will follow a more compact distribution and, in the extreme in some networks, will all be equal to the maximum delay through the network (cycle time). The impact of this type of synthesized network on delay testing will be shown and compared to the case for nonoptimized designs. Finally, recommendations will be made on how network timing optimization can be done in such a way as to minimize the adverse impact on product yield.

Design flow management in the NELSIS CAD framework

Abstract: In this paper a new approach for design flow management is presented. We describe how the inputloutput relations between took can be defined in afIOwmap. For this, several concepts are introduced. such as defrning activities for took, run-time activity identifrcatwn, hierarchical flow graphs, modification versus extension, and the possibility to have loops in the flowmap. We also address tool scheduling and the integration of design flow management in the architecture of a frame-based design system.

Pipe routing-path planning (with many constraints)

Abstract: An implemented system for designing pipe layouts automatically using robot path planning techniques is described. The authors introduce a new approach to pipe layout design automation in which pipe routes are treated as paths left behind by rigid objects (robots). They have implemented this approach in a basic pipe router, which is also described, and have extended this router in order to make it capable of treating a variety of other constraints which are typical of practical pipe layout design problems. These constraints relate to the process carried out in the pipes, to the design of their mechanical support, and to the constructability and the ease of operation and maintenance of the designed pipe systems. >

Grammatical approaches to engineering design, part I: An introduction and commentary

Abstract: A grammar is a definition of a language written in a transformational form. To the extent that design requirements and designed artifacts can be represented by some language, and to the extent that design is a transformation from function to form, grammars might facilitate the development of theories and methods for design. The syntax, lexicon, and semantics of a formal language are analogous to the configuration, components, and behavior of an engineering design. Furthermore, the computational complexity of various grammatical formalisms might provide a foundation upon which to base complexity measures in design. We discuss grammatical formalisms and give examples of how grammars might facilitate design automation.

Hardware technology for Hitachi M-880 processor group

Abstract: The authors explain the high-speed high-density semiconductor technology and high-density installation technology developed for the super-high-speed high-reliability M-880 processor groups. To achieve the design goals, a set of advanced hardware technologies has been developed in such areas as semiconductor, ceramic module board, printed circuit board, electric part, cooling, and power feeding. The innovative hardware technologies have been brought into realization by the development of advanced manufacturing techniques and process techniques in addition to the conventional design automation techniques, inspection and diagnosis techniques, and reliability evaluation techniques. During the design, high-precision high-efficiency design evaluations were carried out using software simulation technologies including a three-dimensional electrical characteristic analyzing program a circuit analyzing program, and a thermal stress analyzing program. >

The IBM High-Level Synthesis System

Abstract: The High-level IBM Synthesis system HIS is the result of ongoing efforts at the T.J. Watson Research Center, the Advanced Business Systems Division and IBM’s Electronic Design Systems. The main goal is to explore design automation for synchronous digital systems at levels above the logic level in a practical environment.

The ADAM design planning engine

Abstract: A novel paradigm for managing the digital process is presented. Under this paradigm, design is seen as a process in which abstract models of design tools are applied to abstract models of design states in a simulated or planning space, until a sequence of design tasks has been constructed to completion. Important parameters of the hypothetical design represented by the terminal states are then estimated. Either the planning is then repeated, or the sequence, or plan, is then executed, or carried out, in an execution space. This execution is monitored for violation of expectations; if violations occur, control is returned to the planner. The knowledge base of the planner is populated with register-transfer level (RTL) concepts for digital system design; it can also be populated with other knowledge sets. The planner forms part of the USC advanced design automation (ADAM) system. >

Applications of VHDL to Circuit Design

Abstract: 1. Switch-Level Modeling in VHDL.- 1.1 Introduction.- 1.1.1 Overview.- 1.1.2 Why Switch-level VHDL Descriptions.- 1.1.3 A Switch-level Modeling Solution in VHDL.- 1.1.4 Choice of Algorithm: Interpretative vs. Compiled, and Global vs. Distributed.- 1.2 Advanced Simulator Programming.- 1.2.1 VHDL Simulation Cycle.- 1.2.2 Variables vs Signals & Predefined Attributes.- 1.2.3 Concurrent vs. Sequential Statements.- 1.2.4 User-defined Packages.- 1.2.5 User-defined Types l.- 1.2.6 Value-System and Resolution Functions.- 1.2.7 Properties of Resolution Functions.- 1.3 Switch-Level Package.- 1.3.1 46-value System.- 1.3.2 Functional Support for the 46-value System.- 1.4 Distributed Algorithm for Pass-transistor.- 1.4.1 Modeling Assumptions.- 1.4.2 Overview of Algorithm.- 1.4.3 Completion of Distributed Algorithm.- 1.5 VHDL Implementation of Distributed Algorithm.- 1.6 Examples of Switch-level Networks.- 1.6.1 One-bit RAM.- 1.6.2 Memory Cell based on two Inverters.- 1.6.3 1,2,4 and 6-bit adders.- 1.6.4 Performance of VHDL Switch-level simulation.- 1.7 Future Research.- 1.7.1 Transistor-network Pattern Recognition.- 1.7.2 More Complex Value-System.- 1.7.3 Hardwired Implementations.- 1.7.4 Analog Models in VHDL.- 1.8 Conclusion.- 1.9 References.- 2. Modeling of Transmission Line Effects in Digital Circuits.- 2.1 Introduction.- 2.2 Underlying Concepts and Structure.- 2.2.1 Superposition.- 2.2.2 Identifying and Structuring Modeling Information.- 2.2.3 General Model Structure.- 2.3 Behavioral Models.- 2.3.1 Losstess Transmission Line.- 2.3.2 Receiver.- 2.3.3 Linear Driver.- 2.3.4 General Driver.- 2.4 Application of Transmission Line Behaviors.- 2.4.1 FET Modeling with the General Driver Model.- 2.4.2 Network Example.- 2.4.3 Simulation Results.- 2.4.4 Limitations and Usage.- 2.5 Summary.- References.- 3. Behavior Modeling of Mixed Analog-Digital Circuits.- 3.1 Introduction.- 3.2 Simulation Model.- 3.2.1 Theory.- 3.2.2 General Model Structure.- 3.2.3 Application to Circuits.- 3.3 Design Verification Methodology.- 3.3.1 Step 1: Cell Level.- 3.3.2 Step 2: Chip Level.- 3.4 Application of Analog-Digital Behaviors.- 3.4.1 Function Generator Model.- 3.4.2 Receiver Model.- 3.4.3 Network Example.- 3.4.4 Simulation Results.- 3.4.5 Limitations.- 3.4.6 Model Usage.- 3.5 Summary.- References.- 4. Modeling of Analog-Digital Loops in VHDL.- 4.1 introduction.- 4.2 AGC Loop Behavioral Models.- 4.2.1 Variable Gain Amplifier.- 4.2.2 Envelope Detector.- 4.2.3 Integrating Capacitor.- 4.3 Application of Automatic Gain Control Loops.- 4.3.1 Network Example.- 4.3.2 Simulation Results.- 4.4 Phase-Locked Loop Behavioral Models.- 4.4.1 Single Shot.- 4.4.2 Phase/Frequency Detector.- 4.4.3 Charge Pump.- 4.4.4 Second-Order Filter.- 4.4.5 Voltage Controlled Oscillator.- 4.5 Application of Phase-Locked Loop.- 4.5.1 Network Example.- 4.5.2 Simulation Results.- 4.5.3 Limitations and Usage.- 4.6 Summary.- References.- 5. Modeling Style Issues for Synthesis.- 5.1 What is HDL Synthesis?.- 5.2 Applying HDL Synthesis Technology.- 5.2.1 The Synthesis Continuum.- 5.2.2 Quality/Productivity Design Automation Acceptance Criteria.- 5.2.3 Practical Considerations.- 5.3 An HDL Synthesis Policy.- 5.3.1 Design Methodology.- 5.3.2 Design Style.- 5.3.3 Supported Language Constructs.- 5.4 Synthesis of Register Transfer Level Constructs.- 5.5 Synthesis Style Issues in VHDL.- 5.5.1 Process Independent Modeling Paradigm.- 5.5.2 Synchronous Operation Through Implicit Storage Elements.- 5.5.3 Partially Asynchronous Operation.- 5.5.4 Asynchronous Operation.- 5.6 A Complete Example.- 5.7 Closing Remarks.- 6. Modeling of Standard Component Libraries.- 6.1 Structure of Model Libraries.- 6.2 Relevant Issues in Logic Simulation.- 6.3 Layers of Abstraction.- 6.4 Independence from Physical Packaging.- 6.5 Strength/Level Values Set Independence.- 6.6 Independence from Timing Parameter Values.- 6.7 Toward a Standard.- 6.8 Summary.- 7. Anomalies in VHDL and How to Address Them.- 7.1 Common Misconceptions about VHDL.- 7.1.1 VHDL Processes and Drivers.- 7.1.2 Initialization of Signals.- 7.1.3 Working Around the Lack of Global Variables in VHDL.- 7.1.4 Use of 'out' and 'buffer' Mode Ports.- 7.1.5 Use of Bus and Register Signals.- 7.1.6 Predefined Signal Attributes.- 7.2 VHDL Language Inconsistencies.- 7.2.1 The Textio Package.- 7.2.2 Spaces in Abstract/Physical Literals.- 7.2.3 Null Slices.- 7.2.4 Slices in Case Statements.- 7.2.5 Resolution Function Parameters.- 7.3 Summary.- 7.4 References.

An object oriented approach to CAD tool control (VLSI)

Abstract: A distributed control mechanism for a large number of VLSI CAD tools is presented. This design framework testbed, named Cadweld, simplifies designer interaction with individual CAD tools and allows arbitrary CAD tools to be easily added or deleted from the design framework. This approach is fundamentally different than many other design framework initiatives that are more concerned with providing a distributed and general data model and tools to support that model. An object-oriented tool integration methodology that treats the tools as objects is presented. This approach simplifies CAD tool control within a design framework, making the framework more general, easier to use, and more capable of supporting a large population of CAD tools. As Cadweld directly extends the unique work of the ULYSSES design framework, the ULYSSES system's strengths and weaknesses are summarized. >

Synthesis From Pure Behavioral Descriptions

Abstract: Rapid progress is being made in LSI design automation as well as in manufacture automation. From the lower to higher parts of the design process, the human designer is being replaced by computer programs. This was once considered impossible, but now the quality of design by computers matches that by human designers.

Design and synthesis of self-checking VLSI circuits and systems

Abstract: Self-checking circuits and systems can detect the presence of both transient and permanent faults. The advantage of such a system is that errors can be caught as soon as they occur, and thus data contamination is prevented. Although much effort has been concentrated on the design of self-checking checkers by previous researchers, very few results have been presented for the design of self-checking functional circuits, and fewer still for the design of self-checking systems. Methods are explored for the cost-effective design of combinational and sequential functional circuits, checkers and systems. >

Applying analogical problem solving to mechanical design

Abstract: Design automation holds great benefits for mechanical-product development. In addition to saving engineers from having to carry out redundant tasks, mechanical design automation can also provide embodiment of knowledge, reduced dowstream manufacturing costs, reduced manual errors and more reliable designs. Most of the approaches to mechanical design automation, thus far, have required a large amount of domain-specific knowledge (e.g. expert systems), and/or have had to presume a particular style of design problem solving (e.g. top-down decomposition, bottom-up constructive). The paper proposes analogical problem solving as an approach for alleviating some of these inherit problems in mechanical design automation. Analogical problem solving is based on the fundamental principle that problem solving can be assisted by the review of solutions to past problems that have been attempted. The technique and issues related to the application of analogical problem solving to mechanical design are presented.

Scheduling and Assignment in High Level Synthesis

Abstract: The continually increasing integration density and chip area will realize integrated circuits with more than a billion transistors in the next 10–20 years. Such complex integrated circuits enable the implementation of complete systems on one single chip. On the one hand this development leads to a growing specialisation and on the other hand to a continually stronger dominated share in design costs. The consequence of this development is the strengthened standardisation of chip structures in the form of standard cell circuits, gate arrays, sea-of-gates or the increasing importance of programmable gate arrays. On the other hand a stronger tendency towards design automation can be observed. In this connection the so-called “high level” synthesis is becoming more and more important. “High-level” synthesis describes the automation of the design above the logic level. While the usual tool support nowadays starts on the logic level, the “high-level” synthesis is understood as the (automatic) generation of a structure description on the register transfer level, resulting from an algorithmic description of behaviour. The advantages of this advanced design support are the low design costs and less design errors.

An open design tool for analog circuits

Abstract: An analog design automation system is presented. The system is capable of designing, analyzing and optimizing analog circuits in MOS, bipolar or BiCMOS technologies. Its main feature is that it is open to the user's expertise. The expertise that can be introduced is knowledge concerning the topology and functionality of a customer circuit, which can be complemented with knowledge about its device sizing sequence. Due to the fact that it is open, it assists and encourages designers in storing their expertise in a structured way, so that it can be reused. The tool includes Monte-Carlo analysis algorithms which ensure an extensive verification and characterization of the design. >

Modeling and simulation of higb-frequency integrated circuits based on scattering parameters

Abstract: We ~esent an approach for accurate modeling and simulation of high-frequency circuits. This capability results from 1) efficient determina tion of scattering matrices of microstrip interconnects using Prony’s method and nonlinear optimization for the evaluation of Som,erfeld integrals, 2) extraction of a generalized charge-based FET model from scattering parameter data and 3) an improved harmonic ba@we technique based on the Newton Projection method. These novel techniques have been integrated into MISIM, a flexible CAD system for design verification and rapid teclmology characterization.

Framework for architecture synthesis of data conversion systems employing binary-weighted capacitor arrays

Abstract: A framework for the architecture synthesis of analog-to-digital (A/D) and digital-to-analog (D/A) conversion systems using binary-weighted C arrays is described. The ability to handle both single and segmented arrays as well as to include calibration networks makes it possible to cover a wide range of specifications. The netlist of the synthesized architecture, including the specifications internally determined for the circuit components, can be interfaced through a dedicated interface management routine with a variety of lower level design environments to achieve a great design flexibility. >

Automating the VLSI design process using expert systems and silicon compilation

Abstract: This paper describes the automatic design of custom integrated circuits from higher level specifications. The paper covers four topic areas: the problem domain and solution approach, higher level synthesis, module to layout automation systems, typically called silicon compiliers, and expert systems which control the design process. In the first three sections, several features of the VLSI problem domain which complicate automation are listed. The VLSI design process is diagrammed and the individual steps described. The term "silicon compilation" is defined to cover the entire process, and definitions for various subcategories of silicon compilers are given. The next Section describes both algorithmic and knowledge-based techniques Which perform higher level synthesis, including area estimation and module binding concurrent with synthesis. Research at Bell Labs, USC, CMU, and in Canada is described, along with other projects. The fifth section discusses the three categories of silicon compilers: commercially available systems, experimental compilers being developed by industry, and artificial intelligence approaches from university research. A survey of several systems is provided. The last section focuses on two systems developed at CMU and USC which plan or control design activities, Ulysses and DPE. Both systems allow the integration of various design automation tools and determine the proper tool invocation to automatically create a design. ADAM takes an autonomous approach, while ULYSSES follows user-defined scripts.

The case for object-oriented databases

Abstract: The drawbacks of relational database management systems (DBMSs) for managing electronic design automation (EDA) data are discussed, focusing on the modeling of data. The object-oriented approach is explained, and it is shown how it meets the needs of EDA. Benchmarking of object-oriented DBMSs is briefly considered, and their use to support cooperative work is examined. >

Hierarchical modeling of the VLSI design process

Abstract: A description is given of the Kinden environment, which combines object-oriented modeling and model-based reasoning to capture, integrate, and manage VLSI design process attributes and hierarchies. Related work is briefly reviewed, and the modeling of the design process is discussed, focusing on the Kinden approach. The model-based reasoning on which Kinden's knowledge-processing architecture is based is described. The present implementation of Kinden is examined. >

Object oriented Lisp implementation of the CHEOPS VLSI floor planning and routing system

Abstract: This paper presents the architecture and capabilities of the CHEOPS Floor Planning and Routing System for macrocell VLSI design, which was implemented in Le-Lisp (@ from INRIA) using Object Oriented Programming. CHEOPS is a highly interactive system providing an integrated set of facilities allowing VLSI designers to cover all steps from initial floorplan evaluation down to final chip composition and detailed routing. It is based on a memory data structure that uniformly models topology and connectivity through all floorplan refinement steps.

Multilevel optimization in the design of a high-performance GaAs microcomputer

Abstract: Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer. >

Cooperative, computer-aided design of scientific visualizations

Abstract: While the field of scientific visualization has grown rapidly over the last decade, the task of designing graphical displays that effectively depict the data to be visualized is still a time-consuming, difficult, and essentially manual process. This paper proposes an approach to partially automating the process through cooperative computer-aided design (CCAD)--a paradigm that combines the strengths of manual and automated design by interspersing guiding design operations by the human user with the exploration of design alternatives by the computer. We demonstrate this approach in the context of the IVE design system--a CCAD environment for the design of scientific visualizations. Given a set of design requirements, the system is able to generate several alternative visualizations using a set of design rules that combine primitive visualization components in different ways. These alternatives are presented graphically to the user, who can browse through them, select the most promising visualization and refine it manually.

GENVIEW: a portable source-level debugger for macrocell generators

Abstract: An effective layout design method for VLSI macrocell is presented in this paper. The method describes a way to write, to test and to validate efficient Full-Custom generators and tilers. First, after a brief overview of the design methodology of tilers, the GENLIB C-library of procedural design functions is described. Second, GENVIEW, a portable and graphic layout debugger for the interactive testing of generators, is detailed.

An efficient layout style for 2-metal CMOS leaf cells and their automatic generation

Abstract: We propose a new layout style that enables an automatic layout synthesizer to take full advantage of the second metal layer available from today’s technology. our style not only facilitates power/grotmd-diffttsion overlapping but also sirnplities the intra-cell routing problem. We have implemented an automatic layout synthesizer, called THEDA.P (Tsing Hua Electronic Design Automation), based on the proposed style. Using the same transistor placement algorithm, THEDA.P outperforms a synthesizer based on [Ueh8 1]’s style by almost 20% in layout mmpacmess across a wide range of SS1 circuits. THEDA.P has been used to build a standard cell library that was previously handcrafted. Results from designing two ASIC modules show that THEDA.P’s layout quality is very competitive.