Showing papers on "Electronic design automation published in 1992"

Method and apparatus for debugging reconfigurable emulation systems

Abstract: An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

A computer-aided design system for microelectromechanical systems (MEMCAD)

Abstract: The authors describe the MIT microelectromechanical computer-aided design system (MEMCAD), in which selected commercial software packages are linked with specialized database and numerical programs to allow designers to quickly perform both mechanical and electrical analyses of structures either described directly, or derived from the design specification (mask data plus process flow). The system architecture, the various modules, and their present status are described, and present system performance is demonstrated with several examples. >

Integrated circuit design optimization using a sequential strategy

Abstract: The authors describe a sequential strategy for designing manufacturable integrated circuits using available CAD tools. Optimizing the performance of complex designs in the presence of unwanted parameter variations can take a prohibitively large number of computer runs. These methods overcome this complexity by combining sequential experimentation with modeling of the CAD simulator output as realizations of stochastic processes. These models give inexpensive approximations that enable location of subregions on which to continue the search for the optimal design. The multistage experimentation reduces the number of simulation runs required to obtain sufficiently accurate approximations. The strategy is able to treat circuits with many parameters, performances, and criteria. Included are two examples where improved designs have been found by these methods. The first is a zero-temperature-coefficient current reference IC. The second is a gallium arsenide voltage level shifter IC with multiple performances of interest. >

Design of delay insensitive circuits using multi-ring structures

Abstract: The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec.tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed. >

Automating the Design of Computer Systems

Abstract: A hierarchical select-and-interconnect methodology for system-level design is described. It extends the flexibility of previous approaches by allowing dynamic subproblem ordering, which is essential for this domain. The design model of M1, a knowledge-based system that implements this approach for small computer systems, is presented. M1's design space covers five microprocessor families, and it has generated hundreds of designs, three of which were built. A set of experiments showing that M1 can be used successfully to design in this complex domain and provides a substantial increase in designer productivity is described. >

Introduction to Synthesis

Abstract: The rapid technological development of the last thirty years has provided means for the design and fabrication of larger and larger electronic systems. This was not possible without equally rapid progress in the development of design methodologies and tools for automated design, which support the designer in the application of these methodologies. Whereas in the early days, design automation was mainly concerned with design verification (circuit and logic simulation, layout verification), later on also with the layout process (physical design starting from a netlist of functional blocks and a corresponding library of predesigned cells), a rapid development of design automation tools can be observed in the late eighties and early nineties that allow for the specification or description of a system at various levels of abstraction in the behavioral domain and for the automated or even automatic implementation of a design starting from this input.

Computer methods for design automation

Abstract: Design automation requires reliable methods for solving the equations describing the performance of the engineering system. While progress has been made to provide good algorithms for polynomial systems, we propose new techniques for the solution of general nonlinear algebraic systems. Moreover, the interval arithmetic approach we have chosen also guarantees numerical reliability. In this thesis we present a number of new algorithms that improve both the quality and the efficiency of existing interval arithmetic techniques for enclosing the solution of nonlinear algebraic equations. More specifically, we propose an exact algorithm for the solution of midpoint preconditioned linear interval equations. We extend existing techniques for automatic compilation of fast partial derivatives to include interval slopes and have conceived a number of graph algorithms to improve their efficiency for general computational graphs. Furthermore, we have devised variable precision techniques to automatically control the required precision based on interval width. Finally, we have unified a number of enclosure languages using denotational semantics. Since design computations can be performed with conservatively bounded models instead of point models, this approach also allows us to develop a framework in which the hierarchical design process can take place and to address the consistency problem associated with incremental refinements. In addition, conservative enclosures are particularly useful when computations are made in a distributed fashion, at different speeds and when communication delays are unpredictable. We believe that since numerical set computations for engineering design fills a void between traditional numerical analysis and discrete mathematics, it promises to be'an exciting new area of research. Thesis Supervisor: Chryssostomos Chryssostomidis Title: Professor of Ocean Engineering

Physics-based electron device modelling and computer-aided MMIC design

Abstract: On overview on the state of the art and future trends in physics-based electron device modelling for the computer-aided design of monolithic microwave ICs is provided. After a review of the main physics-based approaches to microwave modeling, special emphasis is placed on innovative developments relevant to circuit-oriented device performance assessment, such as efficient physics-based noise and parametric sensitivity analysis. The use of state-of-the-art physics-based analytical or numerical models for circuit analysis is discussed, with particular attention to the role of intermediate behavioral models in linking multidimensional device simulators with circuit analysis tools. Finally, the model requirements for yield-driven MMIC design are discussed, with the aim of pointing out the advantages of physics-based statistical device modeling; the possible use of computationally efficient approaches based on device sensitivity analysis for yield optimization is also considered. >

A probabilistic multicommodity-flow solution to circuit clustering problems

Abstract: Circuit clustering, which plays a fundamental role in hierarchical designs, is discussed. Identifying strongly connected components in the circuits can significantly reduce the complexity of the design and improve the performance of the design process. However, there has not been a clear objective function for circuit clustering. A clustering metric based on the random graph model and the ratio cust concept is presented. A probabilistic, multicommodity flow based algorithm is proposed and tested under the clustering metric. Experimental results show that this algorithm generates promising results with respect to the proposed metric. Extensions and directions for future work are also proposed. >

A unified signal transition graph model for asynchronous control circuit synthesis

Abstract: Both low-level (analysis-oriented) and high-level (specification-oriented) models for asynchronous circuits and the environment where they operate, together with strong equivalence results between the properties at the low levels, are described. One interesting side result is the precise characterization of classical static and dynamic hazards in terms of the model. Consequently the designer can check the specification and directly decide if the behavior of any implementation will depend, e.g., on the delays of the signals described by such specification. >

Design process management for CAD frameworks

Abstract: The authors introduce a new mechanism for planning and managing the VLSI design process. The design process manager significantly enhances the capabilities of CAD frameworks, relieving designers from dealing with low-level details, thereby allowing them to concentrate on the more innovative aspects of design. A model for representing design processes is described. To demonstrate the suitability of the design process model, a prototype design process manager, called Minerva, has been developed. Minerva is described. >

LATTIS: an iterative speedup heuristic for mapped logic

Abstract: The author describes heuristic problems for performance optimization of mapped combinational logic, implemented in the system LATTIS (logic area-time tradeoff for integrated systems). LATTIS currently has six transform types: gate repowering, buffer insertion, downpowering of noncritical fanouts of the critical path, gate duplication, DeMorgan's laws, and timing-directed factorization and remapping of subcircuits. From among the transforms applicable on the critical path. LATTIS chooses the one with maximum benefit/cost. Cost is increase in area, and benefit is improvement in local slack, weighted by the number of primary input/outputs affected. The delay-area curves produced by LATTIS for the 70 largest circuits of the 1991 MCNC multilevel combinational logic benchmark set are given. >

Automating High Level Control F'low Transformations For Dsp Memory Management

Abstract: A method and a prototype tool for performing high level control flow transformations for DSP memory management are presented in this paper. Their efficacy is demonstrated by applying them to an industrial regularity detection algorithm, leading to an optimized storage scheme for the large multi-dimensional (M-D) signals within the algorithm. The data flow and control flow of the algorithm are captured by a Polyhedral Dependency Graph. This model has been designed to efficiently capture M-D data flows with a complexity that is independent from size parameters [10, 11]. Using this model, traditional loop-transformations can be generalized and captured in a control flow transformation technique that is amenable to analytical optimization. Performance figures of a CAD tool implementing the transformation method demonstrate the feasibility of this approach for the envisaged application domain.

IBDDs: an efficient functional representation for digital circuits

Abstract: A central issue in the solution of many computer aided design problems is finding a concise representation for circuit designs and their functional specifications. Ordered binary decision diagrams (OBDDs) have recently emerged as a popular representation for various CAD applications such as design verification, synthesis, testing, modeling and simulation. Unfortunately, there is no efficient OBDD representation for many circuits, even in some cases for circuits which perform such apparently simple functions as multiplication. The authors present a new BDD representation scheme, called indexed BDDs (IBDDs), and show that it allows polynomial representations of functions which provably require exponential space using OBDDs. The key idea in IBDDs is to allow multiple occurrences of the input variables, subject to ordering constraints. The authors give an algorithm for verifying the equivalence of two IBDDs and a heuristic for constructing IBDDs for arbitrary combinational circuits. >

Design of multichip modules

Abstract: The process and pitfalls of multichip module (MCM) design, including the constraints, tradeoffs, figures of merit, and considerations which make MCM design a unique interdisciplinary challenge are discussed. The MCM must provide the proper operating environment for the chips it contains. It must also fit the constraints of the system in which it is contained. It must be manufacturable, testable, and repairable. The many aspects of MCM design are described, starting with system benefits, then system and MCM partitioning, chip environment, system constraints, and infrastructure/manufacturing issues. >

Design Automation for Timing-Driven Layout Synthesis

Abstract: List of Figures. 1. Introduction. 2. Delay Estimation. 3. Transistor Sizing Algorithms: Existing Approaches. 4. A Convex Programming Approach to Transistor Sizing. 5. Global Routing Using Zero-One Integer Linear Programming. 6. Timing-Driven CMOS Layout Synthesis. Bibliography. Index.

Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits

Abstract: PREFACE. CHAPTER 1 - INTRODUCTION. 1 Problem Overview: The Design Gap. 1.1 Evolution of the semiconductor industry. 1.2 The design gap. 1.2.1 Time-to-market. 1.2.2 Design complexity. 1.3 Analog design automation. 2 Problem definition. 2.1 Hierarchy, abstraction, and views. 2.2 The AMS design flow. 3 Summary. CHAPTER 2 - A REUSE-BASED DESIGN FRAMEWORK FOR ANALOG ICs. 1 Design automation. 1.1 Preliminary definitions. 1.2 The two sides of automation. 1.2.1 Knowledge-based synthesis . 1.2.2 Optimization-based synthesis. 1.2.3 Quality metrics for analog synthesis . 1.3 Knowledge versus optimization-based synthesis. 2. Circuit reuse. 2.1 Preliminary definitions. 2.2. Digital design reuse. 2.3 Analog design reuse. 2.4 Other approaches to analog reuse. 3 The reuse-based design framework. 3.1 The analog reusable block. 3.2 The design reuse flow. 3.2.1 Adopted synthesis approaches. 3.2.2 The top-down path. 3.2.3 The bottom-up path. 3.2.4 The role of the analog reusable block. 3.3 The design for reusability methodology. 4 Summary. CHAPTER 3 - THE ANALOG REUSABLE BLOCK: BEHAVIORAL FACET. 1 Introduction: Why behavioral descriptions? 1.1 Analog behavioral modeling taxonomy. 2 Facing design reuse. 2.1 The design reuse flow: top-down electrical synthesis. 2.2 The design reuse flow: bottom-up verification. 2.3 Characteristics of the behavioral facet of the AMS reusable block. 3 Case study: a quadrature DA transmit interface. 3.1 System description. 3.2 Reusable macromodels. 4 Summary. CHAPTER 4 - THE ANALOG REUSABLE BLOCK: STRUCTURAL FACET. 1 Introduction. 1.1 Adopted sizing approach. 2 Design knowledge encapsulation. 2.1 Netlist-related elements . 2.1.1 Design variables. 2.1.2 Constraints. 2.2 Testbench setups. 2.2.1Performance feature elements . 2.2.2 Peripheral setup elements. 2.2.3 Component model and process data elements. 2.2.4 Design variables, dependent variables, and constraints . 3 Practical aspects of structural view reuse. 4 Summary. CHAPTER 5 - THE ANALOG REUSABLE BLOCK: LAYOUT FACET. 1 Introduction. 2 Layout retargeting . 2.1 Device mismatch. 2.2 Loading effects. 2.3 Coupling effects. 2.4 Reliability. 2.5 Area occupation. 3 Layout migration. 4 Analog layout strategies. 4.1 Optimization-driven approaches. 4.2 Knowledge-driven approaches. 5 Automated layout generation for design reuse. 6 Layout template: definition and properties. 7 Creating the layout template. 7.1 Device-level layout generation: primitives. 7.1.1 Reuse: migration issues. 7.1.2 Reuse: retargeting issues. 7.1.3 PDLP coding. 7.2 Device-level layout generation: blocks. 7.2.1 Reuse: migration issues. 7.2.2 Reuse: retargeting issues. 7.2.3 PDLB coding. 7.3 Layout template generation. 7.3.1 Reuse: migration issues. 7.3.2 Reuse: retargeting issues. 7.3.3 Layout template coding . 8 Practical implementation of layout-reusable analog blocks. 8.1 Layout languages. 8.2 Implementation examples. 9 Summary. CHAPTER 6 - DESIGN EXAMPLES AND SILICON PROTOTYPE. 1 Introduction. 2 The demonstration vehicle . 2.1 Application area and rationale for architecture selection. 2.2 System specifications and specifications of the analog back-end. 2.3 Hierarchy of the analog back-end. 2.4 Analysis of the analog back-end. 2.4.1 The CT-LP filter. 2.4.2 The PGA. 3 Reusable blocks. 3.1 Reusable blocks: opamps. 3.2 Reusable blocks: analog back-end. 4 Design examples. 4.1 Design example (I): design retargeting and migration of the opamp. 4.1.1 Opamp retargeting in process A (0.35mm). 4.1.2 Opamp migration to process B (0.5mm). 4.2 Design example (II): GSM retargeting o

An integer programming approach to instruction implementation method selection problem

Abstract: A new algorithm for instruction implementation method selection problem (IMSP) in application specific integrated processors (ASIP) design automation is proposed. This problem is to be solved in the instruction set architecture and CPU core architecture designs. First, the IMSP is formalized as an integer programming problem, which is to maximize the performance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. This algorithm will automate the complex parts of the ASIP chip design. >

JESSI COMMON FRAMEWORK Design Management: the means to configuration and execution of the design process

Abstract: The authors outline the basic concepts used in the design management system of the JESSI common framework (JCF). The framework has been developed to aid designers in coping with complex designs existing in the world of CAD. Within the JCF, user, data, and tools that combine to form a design process are configured and executed in a single coherent fashion. Use of this methodology guarantees consistency of the design data. A versioning concept provides the freedom to try out various designs, prior to the selection of the best. The concepts of JCF can be used to save development time. >

Fuzzy controller on FPGA chip

Abstract: A hardware implementation of fuzzy controllers on field programmable gate arrays (FPGAs) is described. FPGAs are semicustom integrated circuits that combine the attractive features of both programmable logic devices and gate arrays. Software for synthesizing fuzzy controllers into Boolean equations was developed. The file that contains the set of Boolean equations is accepted directly by the development system of the FPGA. The development system then produces the necessary code for programming the FPGA chip. The speed of the fuzzy controller is determined by the response time of the FPGA circuit that realizes the Boolean equations. A speed of 50M FLIPS was achieved. The software together with the FPGA development system provide a complete design automation tool for fuzzy controllers. >

The design cube: a new model for VHDL designflow representation

Abstract: Hardware design under the use of the VHSIC hardware description language (VHDL) has to consider three independent property scales that influence the design process from an abstract level to gate level, namely, the design view, the timing aspect, and the value representation. The well-known Y-chart model is not suitable to describe these property scales in a satisfactory way. A new model for the design flow representation with the particular view on VHDL is presented. It is a three-dimensional cube with three coordinates divisions per dimension. Each state of the cube represents a modeling style in VHDL. For the use of more powerful hardware description languages, the cube may be extended to four coordinates per dimension. >

High level synthesis of pipelined instruction set processors and back-end compilers

Abstract: The authors propose a synthesis methodology for high-performance pipelined instruction set processors. Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of the Advanced Design Automation System (ADAS) which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is to perform pipeline scheduling with any fixed instruction-latency, and generate a reorder table for a back-end compiler to resolve potential pipeline hazards existing in the design. Models for performance and cost of both hardware and software are developed to characterize the design space. A synthesis example of a simple instruction set processor illustrates Piper's synthesis capabilities and how the performance and cost of hardware and software are estimated. >

Design assistance for CAD frameworks

Abstract: Decision-making support based on prediction and advice is a fundamental resource that can be used to reduce search in the design space. The authors discuss the advantages of providing CAD frameworks with a general design assistance facility and the basic methodology that should underlay the implementation of such a facility. A general purpose design assistance metal-tool that successfully realizes the proposed methodology is described. This tool has been integrated into the Odyssey CAD Framework. >

Techniques for synthesis of analog integrated circuits

Abstract: The CAD tools that have been developed for automated analog synthesis are reviewed. The synthesis process is described. The major techniques employed by the tools are examined. They are knowledge-based hierarchical design, analytic design, and placement/routing. Critical design issues are identified. It is shown how the technique discussed could be combined in a comprehensive framework supporting design from specification to physical layout. >

Cognitive model of memory for mechanical-design problems

Abstract: Mechanical-design activities can be categorized into two classes: creating new designs for new problems, and modifying old designs to fit new problems. The vast majority of mechanical-design activities can be associated with the latter class. In most cases, it is more effective to modify the design process that creates a mechanical artifact than it is to modify the mechanical artifact itself. A scheme for design automation that uses analogical problem solving as its intelligent agent offers an effective method for solving both classes of mechanical design. It is particularly suited to the latter class of design activities. It relies heavily on a knowledge base for storing design cases generated while solving design problems, and retrieving design cases that are applicable in a new design-problem context. In the paper, a cognitive model of memory for storing design plans is presented. The memory model is four layers deep: product design plans, assembly design plans, component design plans, and recurring-engineering-problem design plans. The storage and retrieval mechanism is based on some of the more popular work found in case-based reasoning. To alleviate the situation in which the user(s) operate (s) in a restricted vocabulary set, a semantic network is integrated into the memory model for use as an elaboration and crossreference mechanism. Mechanica-design plans for products, assemblies, mechanical components and recurring engineering problems can be stored and retrieved from the memory model using information found in the description of the design problem. Sample examples are presented to demonstrate the potential of the memory model.

Application-driven design automation for microprocessor design

Abstract: The authors present an overview of the application-driven design automation system (ADAS) for microprocessor design. ADAS accepts a specification of the instruction set architecture as input, and produces both layout specified in Caltech Intermediate Form, and a reorder table for the language compiler as output. The system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation. Another goal of the project is to determine the feasibility of applying formal methodology to design automation and the usefulness of formal syntax and semantics in defining the meaning of specifications. The system implementation on a real industrial example, the TDY-43 processor, is discussed. >

HiRel-reliability/availability integrated workstation tool

Abstract: The HiRel software tool is described and demonstrated by application to the mission avionics subsystem of the advanced system integration demonstrations (ASID) system that utilizes the PAVE PILLAR approach. HiRel marks another accomplishment toward the goal of producing a totally integrated computer-aided design (CAD) workstation design capability. Since a reliability engineer generally represents a reliability model graphically before it can be solved, the use of a graphical input description language increases productivity and decreases the incidence of error. The graphical postprocessor module HARPO makes it possible for reliability engineers to quickly analyze huge amounts of reliability/availability data to observe trends due to exploratory design changes. The addition of several powerful HARP modeling engines provides the user with a reliability/availability modeling capability for a wide range of system applications all integrated under a common interactive graphical input-output capability. >

VHDL: toward a unified view of design

Abstract: A high-level view of the relevance of and relationships between key events in the development of the very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) is presented. Three phases in the life cycle of the language, the definition, development, and deployment phases, are outlined. The concept of a design information space, a convenient abstraction for categorizing various VHDL efforts and understanding their interrelationships, is introduced. Two representative VHDL examples dealing with performance modeling and testing are discussed. The waveform and vector exchange specification (WAVES) VHDL subset for the exchange of waveform descriptions is described. >