scispace - formally typeset
Search or ask a question

Showing papers on "Electronic design automation published in 1993"


Journal ArticleDOI
TL;DR: A behavioral model of a class of mixed hardware-software systems is presented and a codesign methodology for such systems is defined.
Abstract: A behavioral model of a class of mixed hardware-software systems is presented. A codesign methodology for such systems is defined. The methodology includes hardware-software partitioning, behavioral synthesis, software compilation, and demonstration on a testbed consisting of a commercial central processing unit (CPU), field-programmable gate arrays, and programmable interconnections. Design examples that illustrate how certain characteristics of system behavior and constraints suggest hardware or software implementation are presented. >

280 citations


Journal ArticleDOI
TL;DR: It is shown how identifying clusters in a circuit can simplify two important CAD problems-system-level clustering and module (layout) generation and the essential role such a system could play in aiding the high-level system designer.
Abstract: The authors point out that proper usage of regularity in digital systems leads to efficient as well as economical designs. This important question of regularity extraction is examined, and a general and efficient methodology for component clustering based on the concept of structural regularity is presented. While the concept of regularity can be employed to simplify many problems in the area of design automation, system- and logic-level applications are emphasized here. The authors show how identifying clusters in a circuit can simplify two important CAD problems-system-level clustering and module (layout) generation. A prototype system based on these ideas has been built, and some real-life examples are considered for testing. The results are encouraging; they demonstrate the essential role such a system could play in aiding the high-level system designer. Research is under way to explore some of the other promising applications that such a system could have. >

86 citations


Proceedings ArticleDOI
09 May 1993
TL;DR: A high-level survey of the state of CAD (computer-aided design) for analog and mixed-signal ICs is presented, focusing on synthesis-related work (cell-level and system-level synthesis), with some opinions on how well the author is doing and where he appears to be heading.
Abstract: A high-level survey of the state of CAD (computer-aided design) for analog and mixed-signal ICs is presented, focusing on synthesis-related work (cell-level and system-level synthesis). Both circuit synthesis and layout and system synthesis and layout are considered. Experimental results from some of the Carnegie Mellon University (CMU) tools in each niche of the analog CAD spectrum are used as concrete examples of what the author does (and does not yet) believe can be automated. It is noted that the growing presence of analog functions on chip and the market pressure to decrease design time for new mixed-signal ASICs (application-specific integrated circuits) have forced industry and academia to confront a range of challenging analog design automation problems. The author offers some opinions on how well he is doing and where he appears to be heading.

63 citations


01 Jul 1993
TL;DR: The three most popular types of FPGA architectures are considered, namely those using logic blocks based on lookuptables, multiplexers and wide AND/OR arrays, and the emphasis is on tools which attempt to minimize the area of the combinational logic part of a design.
Abstract: Field programmable gate arrays (FPGA ’s) reduce the turnaround time of application-spec@c integrated circuits from weeks to minutes. However, the high complexity of their architectures makes manual mapping of designs time consuming and error prone thereby offsetting any turnaround advantage. Consequently, effective design automation tools are needed to reduce design time. Among the most important is logic synthesis. While standard synthesis techniques could be used for FPGA’s, the quality of the synthesized designs is often unacceptable. As a result, much recent work has been devoted to developing logic synthesis tools targeted to different FPGA architectures. The paper surveys this work. The three most popular types of FPGA architectures are considered, namely those using logic blocks based on lookuptables, multiplexers and wide AND/OR arrays. The emphasis is on tools which attempt to minimize the area of the combinational logic part of a design since little work has been done on optimizing performance or routability, or on synthesis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs.

59 citations


Journal ArticleDOI
TL;DR: An experimental computer-aided design tool that actively assists in conceptual industrial design of consumer electronics products with injection-molded housings is discussed and examples are presented to show that the system can create designs both meaningful to humans and distinctive in style over a range of products.
Abstract: An experimental computer-aided design tool that actively assists in conceptual industrial design of consumer electronics products with injection-molded housings is discussed. This concept phase design tool uses manufacturing, ergonomic, aesthetic, and styling considerations to improve the entire product development process. The model's organization level performs spatial partitioning of components. The surfacing level generates an enclosure for product design. The third level adds style-specific details, and the fourth level applies graphical elements such as color or decals. Examples are presented to show that the system can create designs both meaningful to humans and distinctive in style over a range of products. >

54 citations


Book
11 May 1993
TL;DR: This paper presents a meta-modelling framework that automates the very labor-intensive and therefore time-heavy and expensive process of manually modeling VHDL models.
Abstract: 1. Structured Design Concepts 2. Design Tools 3. Basic Features of VHDL 4. Basic VHDL Modeling Techniques 5. Algorithmic Level Design 6. Data Flow Level Design 7. Detailed Gate Level Design 8. Multi-Level Design 9. Algorithmic Synthesis

50 citations


Proceedings ArticleDOI
10 May 1993
TL;DR: In this paper, the authors explore the need for improved modeling and analysis support to make DFE (design for environment) a practical aspect of integrated product development and propose an integrated life cycle model (ILCM) for design verification.
Abstract: The author explores the need for improved modeling and analysis support to make DFE (design for environment) a practical aspect of integrated product development He points out that an integrated life cycle model (ILCM) for design verification is needed for effective use of DFE in integrated product development The ILCM should be capable of assessing the relative importance of environmental, health, and safety issues associated with all product life cycle stages, should explicitly represent uncertainty, and should allow evaluation of economic impacts associated with product strategy decisions For practical reasons, the ILCM should be available as part of a customized computer-aided design and engineering (CAD/CAE) environment to allow integrated assessment and optimization of strategic decisions One economic modeling approach well-suited to development of an ILCM is dynamic simulation using generic business process models >

39 citations


Journal ArticleDOI
01 Aug 1993
TL;DR: An approach to automating the design of memory-based VLSI architectures for FIR (finite impulse response) filters has been developed and an automatic synthesis of an area-minimized architecture is developed.
Abstract: An approach to automating the design of memory-based VLSI architectures for FIR (finite impulse response) filters has been developed. The automation is based on the exploration of the design space and schemes for efficient memory replacement, algorithm formulation, architecture design, and evaluation method. Various schemes and design considerations were integrated to produce a parameterized MBA (memory-based architecture) that can easily be tuned to various hardware-speed requirements. This MBA is characterized by three design parameters. Differently configured MBAs result from specifying different values for these parameters. Hardware-speed evaluation formulas were established based on the required elements in MBAs. These elements include ROM, adders, and shift registers. These formulas and a cell library of a target technology can be used to design an optimally configured MBA by searching for the best values of the design parameters with the aid of a computer. Using the evaluation formulas and the parameterized architecture, an area-minimized architecture can be synthesized under a speed specification. Based on these results, an automatic synthesis too has been developed. >

39 citations


Journal ArticleDOI
TL;DR: An architectural synthesis approach for a widely used class of digital systems characterized by inherent regularity in their description, which has the advantage that it keeps track of a set of potentially good candidate solutions, rather than narrowing down to a single solution very early in the design process.
Abstract: This paper presents an architectural synthesis approach for a widely used class of digital systems characterized by inherent regularity in their description. This approach relies on a novel modeling or abstraction of the problem domain to facilitate a hierarchical solution method. The modeling is based on exploiting the inherent regularity in the system description to cluster its behavioral operations. The method emphasizes prudent postponement of design decisions until enough physical design information is available to estimate layout effects like wiring; we use well-known area-delay estimators for this purpose. The approach has the advantage that it keeps track of a set of potentially good candidate solutions, rather than narrowing down to a single solution very early in the design process. Through an extensive set of experiments on well-known DSP design examples, we demonstrate the advantages that such distinctive features have to offer; the impact of hierarchy on several important issues, such as interconnection area, extent of design space explored, etc., is presented. >

36 citations



Proceedings ArticleDOI
01 Jul 1993
TL;DR: Dynamically defined flows are introduced as tool-independent flows that are built up, on demand, by designers that can be used to provide a semantically rich means for browsing the design history database and to provide support for multiple design approaches.
Abstract: Many CAD frameworks now use the notion of a design flow to help provide methodology management services. Most flow-based approaches are limited, however, in that they involve a fixed sequence of operations specified in advance, restrict designers to using only those flows, and "hardwire" specific tools to flows. To overcome this, we introduce the concept of "dynamically defined flows" as tool-independent flows that are built up, on demand, by designers. Dynamically defined flows can be used to provide a semantically rich means for browsing the design history database as well as to provide support for multiple design approaches, such as goal-based, tool-based, data-based and plan-based design.

Proceedings ArticleDOI
03 Oct 1993
TL;DR: This work develops methods to improve the statistical timing behavior of a combinational logic circuit, given probability distributions for the gate and wire delays, using a statistical timing analysis technique developed earlier to drive timing optimization in the right direction.
Abstract: High performance circuit design is becoming increasingly important in VLSI design. The most important problem faced in the design of these circuits is to meet a certain performance level. In the past few years CAD algorithms and tools have been well developed that improve the performance of logic circuits in the sense that the worst case delay is minimized. However, manufacturers recognize that worst case delay models are typically pessimistic and the manufactured ICs will have a range of performances reflecting the manufacturing variations. Thus, the real problem that needs to be solved in the performance optimization of these circuits is to maximize the percentage of fabricated circuits that will achieve a certain performance level, as opposed to minimizing the worst case delay which has been the focus thus far. We develop methods to improve the statistical timing behavior of a combinational logic circuit, given probability distributions for the gate and wire delays. This work uses a statistical timing analysis technique developed earlier to drive timing optimization in the right direction to achieve a prescribed goal with the least area overhead. >

Book ChapterDOI
01 Jan 1993
TL;DR: In this article the fundamentals of spectral design methods are reviewed and some new techniques that make application of such techniques to practical problems feasible are presented.
Abstract: Spectral methods have been used for logic design for many years. However, their use was limited to the synthesis and optimization of small digital circuits, due to the enormous complexity in computing the spectra of large logic functions. Recent developments in design automation and logic synthesis have prompted a new look at these methods, with emphasis on developing efficient computational procedures so that these powerful but complex methods can be used for the synthesis and optimization of larger logic networks. In this article we review the fundamentals of spectral design methods and present some new techniques that make application of such techniques to practical problems feasible.

Proceedings ArticleDOI
02 Oct 1993
TL;DR: An initial review of the design theory associated with DC commutator motors is presented in this paper, followed by a detailed description of a computer-aided design package written specifically for this class of motor.
Abstract: An initial review of the design theory associated with DC commutator motors is presented. This is followed by a detailed description of a computer-aided-design package written specifically for this class of motor. The software engineering content is extremely important. Once the engineering design equations are developed and validated, the productivity of the design engineer depends critically on the efficiency and user-friendliness of the software itself. The package described permits the integration of the motor design with the design of the electronic controller, together with the simulation of the whole system. For sizing motors for a particular application, speed of execution and the flexibility to evaluate a wide range of design options and parameter vibrations are essential, while absolute accuracy is only of secondary importance. >

Proceedings ArticleDOI
07 Nov 1993
TL;DR: In this paper, the authors use conformal mapping to generate abstracted models for the electrical parameters of various RLC interconnect cross-sections, including the frequency dependence caused by ground plane proximity and skin effects.
Abstract: Physical interconnect introduces new challenges for parameter extraction and delay calculation for application specific electronic module (ASEM) design automation. Efficiency dictates the precharacterization of extracted electrical parameters in the same manner as application specific integrated circuits (ASICs). However, ASEM interconnect is dominated by frequency dependent LC propagation which makes precharacterization difficult for all possible configurations. Moreover, simulating the transient behavior of the ASEM interconnect for noise and delay analysis requires the combined use of a variety of models and techniques for efficiently handling lossy, low-loss, frequency dependent, and coupled transmission lines together with lumped parasitic elements. We propose to use conformal mapping to generate "abstracted" models for the electrical parameters of various RLC interconnect cross-sections, including the frequency dependence caused by ground plane proximity and skin effects. Along with precharacterized lumped parasitic elements and nonlinear driver and load models, these models are simulated using a generalized time-domain macromodeling approach that can combine different types of transmission line analysis in one simulation environment. An automatic selection mechanism is derived for determination of the best time-domain macromodel for a particular distributed segment.

Proceedings ArticleDOI
17 Oct 1993
TL;DR: This paper will present the main systems using case-based reasoning for design activities followed by a comparative analysis between these systems, and indicate the main directions in CBR for design and will propose to adopt a cognitive approach from knowledge acquisition until the development of real design support systems.
Abstract: Reuse of designs is an important research direction for the future intelligent CAD systems. The main applications of such a research are various, from mechanical systems design (spacecraft, robot, ...) to software design. This paper will present a survey of the use of case-based reasoning (CBR) techniques for intelligent CAD systems in order to reuse designs or parts of designs. First, we will briefly resume some work issued from cognitive psychology, showing the importance of analogical-reasoning for design activities and then the origins of the CBR technology in AI. Second, we will then present the main systems using case-based reasoning for design activities followed by a comparative analysis between these systems. To conclude, we will indicate the main directions in CBR for design and will propose to adopt a cognitive approach from knowledge acquisition until the development of real design support systems. >

Proceedings ArticleDOI
03 May 1993
TL;DR: Two different optimization algorithms, which, together with the SMOS model, can create an efficient CAD environment for integrated circuit designers are presented.
Abstract: With the aid of the SMOS (statistical MOS) model, it is presently possible to simulate random device mismatch effects on the circuit performance. Two different optimization algorithms, which, together with the SMOS model, can create an efficient CAD environment for integrated circuit designers are presented. The goal of these optimizations is for the user to determine the optimal circuit modifications in order to achieve a user specified parametric yield, as well as the nominal circuit specifications. The optimization algorithms use the steepest descent method and the experiment design method with response surface methodology (RSM). Area optimization of a Miller compensated operational amplifier is used as an example. >

Journal ArticleDOI
TL;DR: A structured method for geometric design rule definitions is presented in terms of edge-based constraints, and the tedious and complicated task of specifying detailed design rules in the technology file is eliminated and placed by a simple macro rule file giving a much better overview of the design rules.
Abstract: A structured method for geometric design rule definitions is presented in terms of edge-based constraints. Using this approach, intralayer design rules such as width and spacing of single layers, and interlayer design rules such as clearance, margin, extension, and overlap of two different layers can be specified in terms of two high-level design rule macros only. The tedious and complicated task of specifying detailed design rules in the technology file is thereby eliminated and placed by a simple macro rule file giving a much better overview of the design rules. Efficient rule compilers have been developed to expand these macro descriptions of the design rules onto basic checks for Magic and for corner-based design rule checking. As an example, the MOSIS scalable CMOS design rule set can be described in terms of the two design rule macros only. More complicated design rules, such as conditional and conjunctive design rules, are also discussed. >

Journal ArticleDOI
TL;DR: Software tools that simplify the design automation process, going far beyond schematic capture, permitting a higher-level design, and helping engineers conceptualize the design as well as implement it, are examined.
Abstract: Software tools that simplify the design automation process, going far beyond schematic capture, permitting a higher-level design, and helping engineers conceptualize the design as well as implement it, are examined. Classified as design synthesis systems, these tools can operate at several levels of abstraction. The processes that take place at each of these levels are described. The roles of hardware description languages, top-down design, and synthesis for testability are discussed. >

Proceedings ArticleDOI
09 May 1993
TL;DR: A new definition of fuzzification is proposed that avoids the use of nonlogical concepts such as 'center of gravity' or 'centroid' and a design automation strategy is provided permitting very effective electrical implementation of complex fuzzy systems by means of simple CMOS static current mirrors.
Abstract: A current-mode fuzzy logic controller whose architecture is based on CMOS current mirrors is presented. A new definition of fuzzification is proposed that avoids the use of nonlogical concepts such as 'center of gravity' or 'centroid'. Due to a simple mathematical description of fuzzy logic connectives, a design automation strategy is provided permitting very effective electrical implementation of complex fuzzy systems by means of simple CMOS static current mirrors. Nine rules are programmable by means of current sources. The circuit consumes 2 mA at 5-V power supply for a core area of 0.4 mm/sup 2/. The fuzzy architecture can achieve 10 MegaFLIPS (fuzzy inferences per second). The chip was successfully used in the control of a metallic ball maintained by an electromagnetic field.

Proceedings ArticleDOI
07 Mar 1993
TL;DR: The electrical engineering department of Tennessee Technological University recently introduced a significant amount of electronic design automation into its digital systems curriculum, which is used by a number of classes at both the undergraduate and graduate levels.
Abstract: The electrical engineering department of Tennessee Technological University recently introduced a significant amount of electronic design automation into its digital systems curriculum, which is used by a number of classes at both the undergraduate and graduate levels. The tools include PSpice, Palasm, and Workview, which supply a broad range of important capabilities. How the tools are used in the classroom and how the students have responded are discussed in detail.

Proceedings ArticleDOI
20 Sep 1993
TL;DR: A set of rules are presented, such that, if respected, the VHDL description is synchronous, and the strict notion of synchronism is extended to circuits that can be resynchronized assuming some good timing property.
Abstract: Previously, the authors (Proc. Euro. Design Automat. Conf., pp. 680-681, 1992) defined how the concept of synchronous design can be mapped to VHDL descriptions. Now, they present a set of rules, such that, if respected, the VHDL description is synchronous. They then extend the strict notion of synchronism to circuits that can be resynchronized assuming some good timing property and introduce the concept of cleanliness for this purpose. >

Book ChapterDOI
Wolfgang Ecker1, Sabine März1
26 Apr 1993
TL;DR: The case study demonstrates the advantages of using VHDL for system-level specification and design and describes a design path comprising both manual interaction and state-of-the-art EDA tools.
Abstract: This paper examines a sample top-down design of a simple CPU starting with a system-level specification in VHDL and ending with an RT-level VHDL description that suits a commercial synthesis tool. Based on the requirement specification captured in a natural language, the design process starts with the creation of a system-level VHDL model, continues with several partitioning steps on system level and the transformation step from system down to RT level, and proceeds over several RT-level optimizations to the final VHDL description. Some of the RT-level optimizations are new in this context . The case study demonstrates the advantages of using VHDL for system-level specification and design and describes a design path comprising both manual interaction and state-of-the-art EDA tools .

Proceedings ArticleDOI
03 Oct 1993
TL;DR: This paper presents a comparison of asynchronous and synchronous standard cell implementations for finite state machine with data-path (FSMD) ASICs through independent parallel designs of a 16-bit factoring ASIC.
Abstract: This paper presents a comparison of asynchronous and synchronous standard cell implementations for finite state machine with data-path (FSMD) ASICs. The comparison is made through independent parallel designs of a 16-bit factoring ASIC. A common functional specification, standard cell library, and suite of EDA tools for layout and simulation are used to provide a common basis for comparison. To clarify design goals and provide more data for comparison each design is separately optimized for speed and for area. Timing and area information for each design is tabulated and discussed to illustrate the specific advantages and disadvantages of each approach. >

Journal ArticleDOI
TL;DR: A statistical based, machine learning process that automatically generates the tool control knowledge necessary to drive the design space reasoning mechanism is described, in the form of a fuzzy, linear differential, qualitative model.
Abstract: In this paper, we present a novel model of CAD tool control that can be used in the constraint-directed control of high-level synthesis tools. To enable this control we introduce the concept of a design space reasoning mechanism. We formally describe a statistical based, machine learning process that automatically generates the tool control knowledge necessary to drive the design space reasoning mechanism. The representation of this tool control knowledge in the form of a fuzzy, linear differential, qualitative model is described. Finally, the experimental results obtained using the Magellan system are presented. >

Proceedings ArticleDOI
03 May 1993
TL;DR: A new graph partitioning problem is introduced from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components which are frequently used.
Abstract: A new graph partitioning problem is introduced. It stems from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components (e.g., adders, multipliers, etc.) which are frequently used. Given an arbitrary circuit data flow graph, it is necessary to realize the circuit by appropriately choosing a set of chips from the chip library. In selecting chips from the chip library to realize a given circuit, both the number of chips used and the interconnection cost are to be minimized. The authors' new graph partitioning problem models this chip selection problem. An efficient solution to this problem is presented. >

ReportDOI
01 Aug 1993
TL;DR: An integrated set of Object Oriented Programming (OOP) enhancements proposed for a future revision of the VHSIC hardware Description Language (VHDL) offers inheritance with extension for VHDL record, array and private type declarations, plus multiple inheritance for entities and corresponding architecture bodies, and a class wide dispatching capability for all tagged types and tagged entities.
Abstract: : This report describes an integrated set of Object Oriented Programming (OOP) enhancements proposed for a future revision of the VHSIC hardware Description Language (VHDL). It offers inheritance with extension for VHDL record, array and private type declarations, plus multiple inheritance with extension for entities and corresponding architecture bodies, and a class wide dispatching capability for all tagged types and tagged entities. If these three enhancements are accepted by the IEEE, VHDL based design automation tools can possess new abstract design capabilities for developing and enhancing electronic hardware. Current software languages with OOP capability increase productivity and reuse by enabling the design process to inherit and extend existing data structures and functionality. By selectively inheriting what already exists, the designer minimizes duplication. Functional capabilities and characteristics can be inherited and extended without affecting existing portions of a design. VHDL, IEEE 1076, Design language, Hardware description language, OOP, Object oriented programming.

Journal ArticleDOI
TL;DR: In this paper, an ordering-reshuffle strategy for building BDDs from a net list description is proposed, which dynamically modifies an initial ordering according to the encountered adverse situation to maintain the intermediate BDD under a reasonable size.
Abstract: An ordering-reshuffle strategy for building BDDs from a net list description is proposed. This algorithm dynamically modifies an initial ordering according to the encountered adverse situation to maintain the intermediate BDD under a reasonable size. The effectiveness of this strategy is demonstrated by building common-ordering BDDs for large circuits in the ISCAS85 benchmark including c7552 which hitherto has not been successful.

Proceedings ArticleDOI
02 May 1993
TL;DR: The authors-ENGE The authors is based on a model of reverse engineering in order to incorporate design rationale into the redesign process and consists of three major parts: knowledge acquisition, construction of a default design plan, and case-based redesign.
Abstract: Design-for-assembly (DFA) analysis of a product may indicate shortcomings of a design, without providing specific guidance on redesigns. A computational tool for assisting redesigns of mechanical assemblies for DFA is introduced. The system, named REV-ENGE, is based on a model of reverse engineering in order to incorporate design rationale into the redesign process. The system consists of three major parts: knowledge acquisition, construction of a default design plan, and case-based redesign. The authors emphasize how a design plan, which serves as the basis for constructing a redesign plan, can be generated with user assistance. A simple example of a redesign of a container is illustrated. REV-ENGE produces redesign plans by constructing and modifying the original design plan, and facilitates the redesign process by providing a specific order and design actions to carry out, while considering design rationale. >

Book ChapterDOI
03 May 1993
TL;DR: The main aim of the presented work is to provide a method for smooth combination of different diagnosis techniques, where the use of logic specifications and algorithmic debugging plays an essential role.
Abstract: This paper discusses application of the technique of algorithmic debugging, originating from logic programming, to automatic diagnosis of VLSI digital circuits. In particular, the main aim of the presented work is to provide a method for smooth combination of different diagnosis techniques, where the use of logic specifications and algorithmic debugging plays an essential role. Examples of the application of the proposed method to combinational and to sequential circuits are presented.