Showing papers on "Electronic design automation published in 1994"

A survey of power estimation techniques in VLSI circuits

Abstract: With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed. >

Instruction set definition and instruction selection for ASIPs

Abstract: Application Specific Instruction set Processors (ASIPs) are field or mask programmable processors of which the architecture and instruction set are optimised to a specific application domain. ASIPs offer a high degree of flexibility and are therefore increasingly being used in competitive markets like telecommunications. However, adequate CAD techniques for the design and programming of ASIPs are missing hitherto. An interactive approach for the definition of optimised microinstruction sets of ASIPs is presented. A second issue is a method for instruction selection when generating code for a predefined ASIP. A combined instruction set and data-path model is generated, onto which the application is mapped. >

Techniques for crosstalk avoidance in the physical design of high-performance digital systems

Abstract: Interconnect performance does not scale well into deep submicron dimensions, and the rising number of analog effects erodes the digital abstraction necessary for high levels of integration. In particular, crosstalk is an analog phenomenon of increasing relevance. To cope with the increasingly analog nature of high-performance digital system design, we propose using a constraint-driven methodology. In this paper we describe new constraint generation ideas incorporating digital sensitivity. In constraint-driven synthesis, we show that a fundamental subproblem of crosstalk channel routing, coupling-constrained graph levelization (CCL), is NP-complete, and develop a novel heuristic algorithm. To demonstrate the viability of our methodology, we introduce a gridless crosstalk-avoiding channel router as an example of a robust and truly constraint-driven synthesis tool.

Error Diagnosis for Transistor-Level Verification

Abstract: This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagates mismatched patterns from erroneous outputs backward into the network and calculates circuit regions which most likely contain the error(s). In contrast to previous approaches, the described technique does not depend on a fixed set of error models. Therefore, it is more general and especially suitable for transistor-level circuits, which have a broader variety of possible design errors than gate-level implementations. Furthermore, the proposed method is also applicable for incomplete sets of mismatched patterns and hence can be used not only as a debugging aid for formal verification techniques but also for simulation based approaches. Experiments with industrial CMOS circuits show that for most design errors the identified problem region is less than 3% of the overall circuit.

Configuration-level hardware/software partitioning for real-time embedded systems

Abstract: In this paper, we present an approach to hardware/software partitioning for real-time embedded systems The abstraction level we have adopted is referred to as the configuration level, where hardware is modeled as resources with no detailed functionality and software is modeled as tasks utilizing the resources Through configuration-level analysis, cost and performance tradeoffs can be studied early in the design process and a large design space can be explored Feasibility factor is introduced to measure the possibility of a real-time system being feasible, and is used as both a constraint and an attribute during the optimization process Optimal partitioning is achieved through the use of an existing computer-aided design tool

Rectification of Multiple Logic Design Errors in Multiple Output Circuits

Abstract: This paper presents the EXMalgorithm, which locates multiple logic design errors in a combinational circuit with multiple output. An error possibility index and a six-valued simulation method have been introduced to reduce the number of error candidates without missing real errors. Experimental results have shown that this algorithm locates all errors at high hit ratio for benchmark circuits.

A Vertically-Integrated Tool for Automated Design of ΔΣ Modulators

Abstract: This paper demonstrates the possibility to automate most critical parts of the design of high-resolution interface circuits. We present measurements from CMOS prototypes of a 16bit@16Khz second-order ΔΣ modulator and a 17bit@40Khz fourth-order ΔΣ modulator. Both use fully-differential switched-capacitor (SC) circuits and have been designed in full-custom style with the help of a CAD tool which uses innovative statistical optimization heuristics for high-level synthesis (the calculation of cell specifications from modulator specifications) and cell sizing (the calculation of transistor sizes from cell specifications). This proposed tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced ΔΣ behavioral simulator for monitoring and design space exploration. This tool has enabled us to complete the design of the fourth-order modulator in 3man/week, of which 65% was for the layout.

Virtual hardware for graphics applications using FPGAs

Abstract: The suitability of FPGA devices for implementing graphics algorithms is analysed by a series of experiments. The performance of simple and complicated graphics algorithms on two kinds of FPGAs are compared with the performance of existing custom graphics chips and against general-purpose processors with specialised instruction sets. Various architectures for incorporating FPGA-based systems into graphics workstations are discussed. Finally, a new design method (based on virtual memory) is presented that exploits the dynamically reconfigurable nature of FPGAs. >

Electronic design automation apparatus and method utilizing a physical information database

Abstract: A physical information database (20) is utilized as an interface between a datapath cell library (22) and a number of electronic design automation tools, such as a datapath synthesis tool (24), a chip estimator (30), an HDL generation tool (28), and a datapath compilation tool (26). The physical information database (20) includes global parameters applicable to every cell in the datapath cell library and local parameters defining attributes that are associated with individual cells in the datapath cell library. The physical information database (20) includes a standard format allowing uniform access by the electronic design automation tools.

The design and evaluation of an asynchronous microprocessor

Abstract: AMULET1 is a fully asynchronous implementation of the ARM microprocessor which was designed at Manchester University between 1991 and 1993. First silicon arrived in April 1994 and was found to be functional, demonstrating that asynchronous design of complex circuits is feasible with present day CAD tools. This paper presents the motivation for the work, some of the design choices which were made, the problems which were encountered during the development of the design and the characteristics of the device itself. The future potential for asynchronous circuits is also discussed. >

Modern Vlsi Design: A Systems Approach

Abstract: 1. Digital Systems and VLSI. 2. Fabrication. 3. Logic Gates. 4. Sequential Machines. 5. Subsystem Design. 6. Architecture Design. 7. Chip Planning. 8. Design Examples. 9. Analysis and Synthesis Tools.

Viewing A program Transformation System At Work

Abstract: How to decrease labor and improve reliability in the development of efficient implementations of nonnumerical algorithms and labor intensive software is an increasingly important problem as the demand for computer technology shifts from easier applications to more complex algorithmic ones; e.g., optimizing compilers for supercomputers, intricate data structures to implement efficient solutions to operations research problems, search and analysis algorithms in genetic engineering, complex software tools for workstations, design automation, etc. It is also a difficult problem that is not solved by current CASE tools and software management disciplines, which are oriented towards data processing and other applications, where the implementation and a prediction of its resource utilization follow more directly from the specification.

Power electronics simulation: current progress and future development

Abstract: The paper gives a comprehensive state-of-the-art technology review of power electronics simulation and design automation tools. New trends have been indicated whenever possible. In particular, the discussion is directed toward the development of a new generation of power electronic simulation and design tools. The techniques reviewed include: the state variable approach; nodal analysis; modified nodal analysis; and state space averaging simulation. The future trends discussed include: a unified multi-level mixed-level simulation framework; automatic generation of behaviour models; computer aided synthesis and optimisation design; and expert systems. >

Hardware-Software Co-Design and ESDA

Abstract: Hardware-software co-design is not a new problem; systems with signi cant portions of hardware and software have been designed for decades. Similarly, system design is not new but the prospect of Electronic System Design Automation (ESDA) has received a great deal of recent attention. Several factors have contributed to the growing importance of these areas but two are particularly relevant: Computer-aided design can claim some modest success in responding to the productivity challenge posed by exponential improvements in processing technology. At the same time, time-to-market challenges for system designers require that complex systems of hardware and software be designed and deployed in 18 months. As a result the formerly distant relatives of hardware and software development have now been brought together and the importance of taking a system perspective has been stressed. This abstract will very brie y identify the problems associated with hardware-software co-design and ESDA and will attempt to identify the most promising of the current responses to these problems. To aid in identifying these problems it may be useful to understand two di erent trends in the evolution of design automation. The rst trend is the familiar raising the level of abstraction, which we associate with ESDA, and this will be treated in Section 2 as well as in [4]. The second trend is broadening design coverage, which we associate with hardware-software co-design, and this will be the focus of Section 3 as well as [6].

A methodology for control-dominated systems codesign

Abstract: This paper presents a methodology and a supporting framework for the design of systems composed of hardware and software modules The aim is to define an approach, tailored for control-oriented applications, to manage system cospecification, high-level partitioning, hw/sw tradeoffs and cosynthesis The main goals are always to improve design time and costs by supporting a flexible architectural exploration and to achieve a smooth integration within standard industrial design environments Our research effort focuses on fulfilling the goal of linking high-level specifications to efficient and cost-effective hw/sw implementations by investigating techniques such as synchronous cospecification styles, direct machine code generation as well as exploiting the capability of commercial VHDL synthesizers >

Reuse of design objects in CAD frameworks

Abstract: The reuse of well-tested and optimized design objects is an important aspect for decreasing design times, increasing design quality, and improving the predictability of designs. Reuse spans from the selecting cells from a library up to adapting already designed objects.In this paper, we present a new model for reusing design objects in CAD frameworks. Based on experiences in other disciplines, mainly in software engineering and case-based reasoning, we developed a feature-based model to describe design objects and their similarities. Our model considers generic modules as well as multi-functional units. We discuss the relationships of the model to design process and to the configuration hierarchy of complex design objects. We examined our model with the prototype system RODEO.

Random Generation of Test Instances for Logic Optimizers

Abstract: The attempt of using random test circuits for evaluating the performance of logic optimizers like SIS is apparently new. To generate "reasonable" random circuits, we propose the random applications of several transformation rules to an initial circuit instead of the obvious method, random placement of connections. A preliminary experiment has been conducted on SIS's responses against such random circuits. SIS shows considerably different performances for different circuits generated from the same original circuit.

Capturing Design Dynamics the Concord Approach

Abstract: ‘Computer-Supported Cooperative Work’ is a young research area considering applications with strong demands on database technology. Especially design applications need support for cooperation and some means for controlling their inherent dynamics. However, today’s CAD systems mostly consisting of a collection of diverse design tools typically do not support these requirements. Therefore, an encompassing processing model is needed that covers the overall design process in general as well as CAD-tool application in particular. As a consequence, this model has to be rich enough to reflect the major characteristics of design processes, e.g., goal-orientation, hierarchical refinement, stepwise improvement as well as team-orientation and cooperation. The CONCORD model that will be described in this paper, reflects the distinct properties of design process dynamics by distinguishing three levels of abstraction. The highest level supports application-specific cooperation control and design process administration, the second considers goal-oriented tool invocation and work-flow management while the third level provides tool processing of design data. To achieve level-spanning control, we rely on transactional facilities provided at the various system layers. 1. Introduction & Overview Facing the growing complexity of technical products, the process of design is typically carried out by a team of cooperating designers rather than by a single person. Several methodologies have been developed to structure the overall design process and to support designers working on partial design problems and cooperating with each other, e.g., by negotiating their individual design goals or by exchanging their partial results. However, today’s CAD systems typically do not support cooperative work in a satisfactory manner. Exchange of preliminary results is usually done without system support and control. In larger design teams this causes inconsistencies in design objects which must be resolved by hand with a considerable overhead. In our opinion, such problems can be faced by extending database technology with ‘cooperation capabilities’.

PROTEUS: programmable hardware for telecommunication systems

Abstract: This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed. >

System and method for generating a template for functional logic symbols

Abstract: The system and method improves Electronic Design Automation practices by creating a data template representing pins, elements, and dependencies for numerous components in the same functional class. A pin having the same function is represented once on the data template even if the pin name is different. Sequences of component pins having the same function are combined and are represented by a single pin on the data template. The performance of functional logic symbol generation systems increases significantly because the data template enables the creation of functional logic symbols to be accomplished quickly, accurately, and consistently.

Analog hardware description languages

Abstract: With the growing trend in ASIC design to include more analog functions on chip, various design support and automation efforts have arisen to address the analog design concerns. Existing hardware description languages have been widely used for design representation, documentation and transfer mainly in the digital domain, with standards such as VHDL being fairly mature. In this paper we present two efforts that are underway in developing standardized analog hardware description languages. One of these is a new language called MHDL for analog and mixed-signal representation while the second is aimed at providing analog extensions to the existing VHDL standard. >

Design of a pipelined datapath synthesis system for digital signal processing

Abstract: In this paper, we describe the design of SODAS-DSP (Sogang Design Automation System-DSP), a pipelined datapath synthesis system targeted for application-specific DSP chip design. Through facilitated user interaction, the design space of pipelined datapaths for given design descriptions can be explored to produce an optimal design which meets design constraints. Taking SFG (Signal Flow Graph) in schematic as inputs, SODAS-DSP generates pipelined datapaths through scheduling and module allocation processes. New scheduling and module allocation algorithms are proposed for efficient synthesis of pipelined hardwares. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equidistribution of operations among pipeline partitions is adopted as the objective function. Module allocation is performed in two passes: the first pass for initial allocation and the second one for seduction of interconnection cost. In the experiments, we compare the synthesis results for benchmark examples with those of recent pipelined datapath synthesis systems, Sehwa and PISYN, and show the effectiveness of SODAS-DSP. >

Experience with Image Compression Chip Design Using Unified System Construction Tools

Abstract: This paper describes the use of Unified System Construction tools under development at the University of Southern California. The goal of the project is to automate the construction of heterogeneous, application-specific systems. Key elements of the USC system include multiprocessor synthesis, multi-chip datapath synthesis, memory-intensive synthesis, and multi-chip partitioning. The tools were applied to design of an image compression chip set, and results of using these tools are reported on here. Our results are comparable to manual designs reported in the literature.

ALADIN: a multilevel testability analyzer for VLSI system design

Abstract: In order to cope with tomorrow's challenges in the microelectronic market, the reliability of the first phases of the design process must be improved. The possibility of applying techniques for testability analysis at these abstract design levels can considerably help in achieving this goal, reducing at the same time system design costs. In this paper we introduce a novel approach for the application of functional testability at system design level and demonstrate the possibility of its application in an industrial environment. Testability conditions referring to both regular and irregular topologies have been defined, formalized and inserted into the knowledge base of the expert system, ALADIN. This tool operates as a testability analyzer able to identify critical areas for testability in designs whose functional modules and local interconnections are known and described in standard VHDL. The architecture of the tool has been defined in order to satisfy the users' requirements including the integrability into a standard CAD design flow through standard I/O interfaces. Then its application to both a regular and an irregular topology are presented in order to show on real examples which testability conditions apply, and how the tool operates in order to reach the testability assessment. From these industrial case studies, figures of merit are derived from which it is possible to evaluate the importance of the application of such a methodology to system level design. >

Design of heterogeneous ICs for mobile and personal communication systems

Abstract: Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of flexibility, performance and power dissipation, are driving the development of integrated circuits into the direction of heterogeneous single-chip solutions. New IC architectures are emerging which contain the core of a powerful programmable processor, complemented with dedicated hardware, memory and interface structures. In this tutorial we will discuss the real-life design of a heterogeneous IC for an industrial telecom application: a reconfigurable mobile terminal for satellite communication. Based on this practical design experience, we will subsequently discuss a methodology for the design of heterogeneous ICs. Design steps that will be addressed include: system specification and refinement, data path and communication synthesis, and code generation for embedded processor cores.

A formal basis for design process planning and management

Abstract: In this paper we present a design formalism that allows for a complete and general characterization of design disciplines and for a unified representation of arbitrarily complex design processes. This formalism has been used as the basis for the development of several prototype CAD meta-tools that offer effective design process planning and management services.

Development and evaluation of a distribution automation system for an Indian utility

Abstract: This paper describes a study conducted by the Andhra Pradesh State Electricity Board (APSEB), India, and ECC, Inc., USA for the design of a distribution automation system (DAS). Distribution automation functions applicable to an Indian electric utility were identified. Communications technologies that are capable of meeting DAS requirements were evaluated, and a communications system suitable for India was defined. A benefit/cost analysis was performed; first for a basic DAS and then for additional distribution automation functions. >

Improved delay and current models for estimating maximum currents in CMOS VLSI circuits

Abstract: Excessive voltage drops in power and ground (P&G) buses of CMOS VLSI circuits can severely degrade both design reliability and performance. Maximum current estimates are needed in the circuit to accurately determine the impact of these problems. In a previous paper by the authors (see Design Automation Conf., p. 2-7, June 8-12, 1992), a pattern-independent, linear time algorithm (iMax) is described that is very effective in estimating the maximum current waveforms at various contact points in the circuit. In the aforementioned paper, the algorithm was demonstrated for simple gate delay and current models. In this paper, we first derive expressions for modeling delays and current waveforms for a general gate and then describe how the algorithm can be extended under more general models. >