Showing papers on "Electronic design automation published in 1997"

Embedded logic analyzer for a programmable logic device

Abstract: A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made. The EDA tool then directs the logic analyzer to unload the data from its capture buffer and then displays the data on the computer. The logic analyzer circuit may then be rearmed to capture another sequence of sample values. The trigger condition may be changed without recompiling. The design may be recompiled with new logic analyzer parameters to debug a different portion.

Recent developments in high-level synthesis

Abstract: We survey recent developments in high level synthesis technology for VLSI design. The need for higher-level design automation tools are discussed first. We then describe some basic techniques for various subtasks of high-level synthesis. Techniques that have been proposed in the past few years (since 1994) for various subtasks of high-level synthesis are surveyed. We also survey some new synthesis objectives including testability, power efficiency, and reliability.

Structured design of microelectromechanical systems

Abstract: In order to efficiently design complex microelectromechanicalsystems (MEMS) having large numbers of multi-domain components,a hierarchically structured design approach that iscompatible with standard IC design is needed. A graphical-basedschematic, or structural, view is presented as a geometrically intuitiveway to represent MEMS as a set of interconnected lumped-parameterelements. An initial library focuses on suspended-MEMStechnology from which inertial sensors and other mechanicalmechanisms can be designed. The schematic representationhas a simulation interface enabling the designer to simulate thedesign at the component level. Synthesis of MEMS cells for commontopologies provides the system designer with rapid, optimizedcomponent layout and associated macro-models. Asynthesis module is developed for the popular folded-flexuremicromechanical resonator topology. The algorithm minimizes acombination of total layout area and voltage applied to the electromechanicalactuators. Synthesis results clearly show the designlimits of behavioral parameters such as resonant frequency for afixed process technology.

Access restriction to circuit designs

Abstract: A computerized system restricts full revelation of certain information to a user, while also performing limited processing of the information for the user for evaluation. The information is encrypted and therefore may be widely distributed without fear of revelation. An authorization code from the user specifies the type(s) of processing that are permitted, wherein different types of processing produce different type(s) of output that reveal to different degrees the information. The type(s) of output include output which represent more than mere reproduction of the information. A particularly appropriate implementation of the present invention is in the area of Electronic Design Automation (EDA) for logic design.

Designing automation to reduce operator errors

Abstract: This paper describes an approach to dealing with mode confusion errors by first modeling blackbox software behavior and then using analysis methods and tools to assist in searching the models for predictable error forms, i.e., for features that contribute to operator mistakes. The analysis results can be used to redesign the automation, to change operator training and procedures, or to design appropriate human-computer interfaces to help avoid mistakes. The approach requires a model of the blackbox behavior that is both formal and easily readable and reviewable by humans. The models we use are part of the software specifications in a methodology called SpecTRM (Specification Tools and Requirements Methodology) and thus the analysis is done directly on the system requirements specification and does not require extra modeling effort.

Core design and system-on-a-chip integration

Abstract: IBM's experience with core-based designs provides insight into methodology, SOC design styles, core design trade-offs, and ASIC design processes. The authors describe a prototype cosimulation system developed for the PowerPC core and present SOC designs to illustrate their methods.

Logic synthesis for large pass transistor circuits

Abstract: Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. The authors motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multistage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. They show that the proposed approach allows one to make logic-level optimizations similar to the traditional multi-level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do nor have any equivalent in the traditional approach. They also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that the technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of their knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

A review of EMI shielding and suppression materials

Abstract: The effect of growth of the electronics industry and the widespread use of electronic equipment in communications, computation, automation, biomedicine, space and other areas has led to many electromagnetic interference (EMI) problems for the designers as their systems/subsystems operate in close proximity. It is likely to become more severe in the future, unless designers follow EMI control methodology/techniques to meet the EMC requirements during the design stage itself. The elimination or suppression of EMI should be a prime objective of the designer. In this paper the authors have made an attempt to present technical data/details of various EMI suppression materials/devices available in the market and simplified the job of designers in verifying different catalogues which may be directly applied to the problem and harden the system/subsystem in compliance with EMC standards. As the design and development proceeds, the number of available noise reduction techniques also decreases and at the same time the cost of the mitigating noise goes up. Hence selecting the right component at the right time is essential. This paper gives a quick reference to the designer to reduce the noise at source level in the system during the design and development stages by choosing the appropriate component/device and fixing it correctly into the problem.

A framework of virtual design for product customization

Abstract: One major challenge of mass customization is how to meet two seemingly conflicting goals, namely satisfying individual customers' needs while keeping mass production efficiency. In order to help customers to select the appropriate product family so that the closest variant can be quickly generated and delivered, this paper proposes a virtual design approach by developing virtual prototypes to represent the product platform. With virtual prototypes, assessments of constant delivery can be made to facilitate the selection and negotiation process between sales and customers, thus enabling better informed customization design. The primary goal of virtual design for mass customization is to provide a multidisciplinary design definition at the product family level, and the closest product variant can be rapidly generated. Furthermore, a scenario based simulation environment for design trade-off can be done in an integrated framework. Such a design environment facilitates capturing customer needs and appropriately informing them of the capability of the firm. Ultimately, through virtual design, customers can directly interact with the CAD systems to make trade-offs among factors that are important to them. These factors can be performance, aesthetics, value, cost, urgency, and others. This paper discusses the technical issues that need to be addressed in realizing virtual design and an example is presented to illustrate the proposed approach.

Tools and methodologies for low power design

Abstract: Designing for low power has becomeincreasingly important in a wide variety ofapplications, including wireless telephony, mobilecomputing, high performance computing, and highspeed networking. Despite reductions in powersupply voltages, power consumption continues to riseand demands increased support from EDA tools andmethodologies. Various tools have emerged toaddress different levels of the power problem, yetconventional methodologies often focus on the lowleverage aspects. This paper will survey existingcommercial tools used in low power design andpresent them in the context of an architecture focusedlow power design methodology.

An agent-based paradigm for building intelligent CAD systems

Abstract: The present paper proposes a hybrid approach based on reactive agent technology as a post-object paradigm for building intelligent CAD systems. It represents an evolution of previous positions and articles by the authors motivated by a clear need to provide forms of active support for the design process rather than seeking full design automation purposes. Key concepts about agency and reactivity, as well as their usefulness in design systems, are presented. Also a basic tool called XLOG+, for developing agent-based systems, comprising logic and object oriented approaches, is discussed. Finally, the proposed hybrid agents are embedded in a new integrated CAD system architecture and an implemented prototype example in the area of solid modelling is briefly presented.

Supporting situation awareness in aviation systems

Abstract: Situation awareness is recognized as one of the most critical aspects in the aviation domain. Many features of our high technology environment can act to subtly degrade situation awareness, however, including high levels of complexity, out-of-the-loop performance decrements resulting from automation, and lack of synergy in human and machine decision making. An approach that seeks to design for situation awareness enhancement is explored as a viable alternative to traditional automation approaches.

An architecture to support incremental automation of complex systems

Abstract: Operators and domain practitioners often complain that automation is brittle, opaque, and 'not worth the effort' to use. This paper reviews automation problems and methods for the design of 'cognitive automation.' Cognitive automation is software intended to automate cognitive activities, such as situation assessment, monitoring, and fault management, that are currently performed by human operators. Limitations of current knowledge engineering methods-the key to robust cognitive automation-are presented. With this background, a design methodology and automation concept-incremental automation-are proposed. Incremental automation is software, which by design, serves as a cognitive apprentice to the operations staff of a complex dynamic system. Over time, as operations personnel refine and extend it, incremental automation accumulates knowledge that covers a broad range of operational experience. Furthermore, and again by design, the structure and processing used by incremental automation closely emulates structures and processes used by expert operators, thus facilitating software that is easy for domain practitioners, including operators, system designers, and management, to understand, repair, and enhance. APPRENTICE is the computational form of the methodology. This paper concludes with a description of an architecture to support incremental automation and its application in a NASA satellite ground control system.

CAD and foundries for microsystems

Abstract: Besides foundry facilities, Computer-Aided Design (CAD)tools are also required to move microsystems from researchprototypes to an industrial market. Currently available CADtools need extensions before they can be used for theautomated design of micromachined devices.This paper presents a low cost access to microsystemtechnology (MST), applied by the CMP service, and based onthe use of existing microelectronics production lines, withadditional post-processing for microsystem specific 2D and3D structures, and a global CAD approach for the design andsimulation of microsystems applied to currently availablecommercial CAD tools, e.g. Mentor Framework, in order toensure a continuous flow from the design to themanufacturing.

A Cadence-based design environment for single flux quantum circuits

Abstract: The semiconductor industry standard computer-aided-design (CAD) tool Cadence has been calibrated for a 3 /spl mu/m Niobium technology in order to design and build superconductive single flux quantum (SFQ) circuits. The top-down design methodology includes Verilog functional simulation, schematic capture, graphic layout, functional verification, design rule checking, electrical rule checking, and layout-vs.-schematic verification. This design framework has been used successfully at the University of Rochester in designing more than 15 elementary SFQ cells and three large scale digital and mixed-signal SFQ circuits, demonstrating significant improvement in both design efficiency and accuracy.

Data Parallel Neural Dynamics Model for Integrated Design of Large Steel Structures

Abstract: We have two objectives in creating novel design theories and computational models : automation and optimization. These two aspects are particularly important in design of complex and large engineering structures. In this article, a robust data parallel neural dynamics model is presented for discrete optimization of large steel structures based on the AISCASD or LRFD specifications. The computational model has been implemented on a CM-5 supercomputer and applied to integrated minimum-weight design of two steel high-rise building structures. The largest example is a 144-story modified tube-in-tube super-high-rise building structure with 20,096 members. Optimization of such a large structure subjected to the highly, nonlinear constraints of actual design codes, such as the AISC LRFD code, where nonlinear second-order effects have to be taken into account, has never been attempted before. The computational model developed in this research finds the minimum-weight design for this very large structure subjected to multiple dead, live, and wind loadings in three different directions automatically. This research demonstrates how a new level in design automation is achieved through the ingenious use of a novel computational paradigm and new high-performance computer architecture.

Understanding the nature of design

Abstract: AI in design includes the modeling of designer activity, the representation of designer knowledge, and the construction of either systems that produce designs or systems that assist designers.1 Through these activities, we hope to gain better insight both into the nature of design processes and representations, and into methods for developing systems to support design activities. More generally, these studies contribute to our understanding of intelligent behavior. This area has various names, including AI in Design (AID), Knowledge-Based Design Systems (KBDS), Intelligent CAD (IntCAD or ICAD), and Knowledge Integrated CAD (KIC).2 Areas of related work include concurrent engineering, simultaneous engineering, and concurrent design. Design researchers use a variety of AI techniques, such as constraint satisfaction, search, negotiation, and knowledge representation. Because design is inherently multidisciplinary, researchers often draw on results from fields such as cognitive psychology, decision theory, optimization, language theory, and architecture.3,4 The task of design (as opposed to, say, diagnosis) and the domains in which design is being done (for example, computer design and bridge design) influence how these techniques are used.

Multimodal interface for a virtual reality based computer aided design system

Abstract: Generation of geometric shapes called "geometric concept designs" via the multimodal user interface of a virtual reality (VR) based system motivates the current research. In the VR system, geometric designs can be more effectively input into the computer in a physically intuitive way (using voice, hand motions, and gestures-just as a person would communicate ideas to another person). Although the dimensions inputted may be imprecise, this approach is useful for concept shape generation since at this stage dimensions need not be exact. The paper focuses on determining the requirements for the multimodal user interface and assessing the applications of different input and output mechanisms in the virtual environment (VE). Based on the results of these investigations, a VR-based computer-aided design (CAD) system for the conceptual shape design will be implemented in the current research. Once designers use the system that we are developing, the interface requirements determined in the current paper may be verified or refined. The objectives of the research are to expand the frontiers of product design and establish a new paradigm for the VR-based conceptual shape design system.

CAD tools for area-distributed I/O pad packaging

Abstract: The use of area interconnect packaging in high frequency microprocessors is motivated by its high-bandwidth and good power distribution capability. An MCM packaging scheme based on area-distributed I/O pads serves as the foundation of the PUMA project at the University of Michigan. Area interconnect facilitates high I/O counts, shorter interconnect routes, smaller power rails, and better thermal conductivity, all of which are important in high clock-rate digital systems. This paper introduces recently developed CAD tools that aid in the design of flip-chip area-interconnected integrated circuits. The tools permit the designer to place and route area bond pads as dictated by the layout of the microprocessor. System level issues, such as adequate power distribution and placement of area pad buffers, are addressed. The CAD system includes area pad power analysis, floorplanning, and routing tools.

Technology mapping for speed-independent circuits: Decomposition and resynthesis

Abstract: This paper presents theory and practical implementation of a method for multi-level logic synthesis of speed-independent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but is technology independent. The proposed method performs both combinational (inserting new gates) and sequential (inserting new memory elements) decomposition of complex gates in a given standard cell library, while preserving original behaviour and speed-independence. The algorithm applies known efficient algebraic factorization techniques from combinational multi-level logic synthesis, but achieves also boolean simplification and sequential decomposition. The method allows sharing of decomposed logic.

Simulation-based robot cell design in AdeptRapid

Abstract: In order to rapidly design and deploy automated manufacturing systems, simulation-based design and optimization software will become increasingly essential. Using a simulator to design alternative concepts and communicate them to system integrators and end-users can effectively reduce the overall time needed to install flexible automation. Robots do not work in isolation. Simulation based cell design must pay significant attention to the design and operation of various peripherals. Object oriented techniques seem to be a clear win in cleanly implementing not only simulated robots but also libraries of cell peripherals. Overall cycle time of a robotized cell must be predictable to within a few percent. This need produces requirements not only on accurately predicting robot motion times, but also timing associated with cell peripherals such as grippers, conveyors, and parts feeding schemes. With all these items accurately modelled, the system can perform optimizations to automatically search for superior designs. This paper introduces AdeptRapid, a simulation based design system that has been developed by the SILMA division of Adept Technology, Inc.

Designing high performance CMOS microprocessors using full custom techniques

Abstract: In this paper, we describe a full customCMOS design methodology and supporting CADtechnologies used to develop ALPHA and StrongARMmicroprocessors at Digital Semiconductor The paper issubdivided into four parts, starting with a description ofthe design methodology and general CAD flowsAdditional sections focus on two particular areas ofinterest: high performance low-power and full customdesign benefits and verification issues

P2Lib: process-portable library and its generation system

Abstract: This paper describes a process-portable library and its generation system called P2Lib. From technology parameters which characterize a fabrication process, P2Lib generates a complete set of standard cell libraries for logic synthesis, logic simulation, and layout synthesis. A distinctive feature of P2Lib is the rapid characterization of timing and power dissipation by an analytic-oriented method, as well as the accurate characterization by circuit simulation. A designer can quickly create a library under various operating conditions and process specifications, so that he can examine his design with CAD tools. The quality of generated libraries (layout and timing) are discussed and a design example with P2Lib is presented.

PROPHID: a data-driven multi-processor architecture for high-performance DSP

Abstract: PROPHID is a design method for high-performance systems with a focus on high-throughput signal processing applications. It makes use of a novel stream-based multi-processor architecture, consisting of data-driven autonomous processors interconnected by a programmable connection network. The key element is the communication arbiter which controls the flow of data between processors. Variable rates and data-dependent processing times are handled efficiently by performing scheduling at run time. We give an overview of the characteristics and advantages of the architecture as well as some implementation results.

Evolutionary methods for modelling and control of linear and nonlinear systems

Abstract: The aim of this work is to explore the potential and enhance the capability of evolutionary computation for the development of novel and advanced methodologies for engineering system modelling and controller design automation. The key to these modelling and design problems is optimisation. Conventional calculus-based methods currently adopted in engineering optimisation are in essence local search techniques, which require derivative information and lack of robustness in solving practical engineering problems. One objective of this research is thus to develop an effective and reliable evolutionary algorithm for engineering applications. For this, a hybrid evolutionary algorithm is developed, which combines the global search power of a "generational" EA with the interactive local fine-tuning of Boltzmann learning. It overcomes the weakness in local exploration and chromosome stagnation usually encountered in pure EAs. A novel one-integer-one-parameter coding scheme is also developed to significantly reduce the quantisation error, chromosome length and processing overhead time. An "Elitist Direct Inheritance" technique is developed to incorporate with Bolzmann learning for reducing the control parameters and convergence time of EAs. Parallelism of the hybrid EA is also realised in this thesis with nearly linear pipelinability. Generic model reduction and linearisation techniques in L2 and L∞ norms are developed based on the hybrid EA technique. They are applicable to both discrete and continuous-time systems in both the time and the frequency domains. Superior to conventional model reduction methods, the EA based techniques are capable of simultaneously recommending both an optimal order number and optimal parameters by a control gene used as a structural switch. This approach is extended to MIMO system linearisation from both a non-linear model and I/O data of the plant. It also allows linearisation for an entire operating region with the linear approximate-model network technique studied in this thesis. To build an original model, evolutionary black-box and clear-box system identification techniques are developed based on the L2 norm. These techniques can identify both the system parameters and transport delay in the same evolution process. These open-loop identification methods are further extended to closed-loop system identification. For robust control, evolutionary L∞ identification techniques are developed. Since most practical systems are nonlinear in nature and it is difficult to model the dominant dynamics of such a system while retaining neglected dynamics for accuracy, evolutionary grey-box modelling techniques are proposed. These techniques can utilise physical law dominated global clearbox structure, with local black-boxes to include unmeasurable nonlinearities as the coefficient models of the clear-box. This unveils a new way of engineering system modelling. With an accurately identified model, controller design problems still need to be overcome. Design difficulties by conventional analytical and numerical means are discussed and a design automation technique is then developed. This is again enabled by the hybrid evolutionary algorithm in this thesis. More importantly, this technique enables the unification of linear control system designs in both the time and the frequency domains under performance satisfaction. It is also extended to control along a trajectory of operating points for nonlinear systems. In addition, a multi-objective evolutionary algorithm is developed to make the design more transparent and visible. To achieve a step towards autonomy in building control systems, a technique for direct designs from plant step response data is developed, which bypasses the system identification phase. These computer-automated intelligent design methodologies are expected to offer added productivity and quality of control systems.

Overview of microelectromechanical systems and design processes

Abstract: New design tools and automation strategies are neededto create robust, cost-effective, and manufacturable micro-machineddevices and systems. Some of the design automationissues include mixed-technology simulation, materialproperty prediction in the micron-size regime, self-consistencyin coupled electromechanical devices, integratedmodeling environment, micro-fluid modeling, and synthesisof device geometries and process flows. Advancement inthese areas will path the way to full-scale maturity of theMEMS field.

Probe points and markers for critical paths and integrated circuits

Abstract: A method for automated placement of markers or probe points adjacent to critical timing paths in an integrated circuit design. The markers aid in identifying critical path interconnect lines for purposes of failure analysis or design verification. In a method according to the invention, timing information related to various signal paths in an integrated path is analyzed to isolated critical timing paths. Once a signal path is determined to be a critical timing path, layout data for the critical path is extracted from a layout database. An unused area(s) is then located adjacent to the critical path. Marker information is next inserted into the unused area(s) of the layout database. The act of inserting marker information is performed by a specialized software tool capable of modifying a layout database. Alternatively, existing automated floorplanning or layout tools, or other electronic design automation (EDA) tools, whether proprietary or industry standard, are modified to insert the marker information. The marker information causes markers to be fabricated at strategic points along the critical path in the unused areas without violating design rules. Hence, upon visual inspection of the integrated circuit, a failure analyst can readily locate the markers and identify critical paths.

Overhead intrabay automation and microstocking. A virtual fab case study

Abstract: As the need for higher efficiencies in semiconductor manufacturing intensifies, the importance of effective intrabay automation increases. Direct delivery overhead zero foot print intrabay automation, coupled with microstocking of WIP will be a means to maximize the throughput of fully automated fabs. Microstocking can be practically implemented in the following four ways. The first instance of microstocking is found on a process tool that has more than one Input/Output (I/O) port. Another form of microstocking is the internal tool buffer commonly found on vertical furnaces and wet processing benches. A third manifestation of microstocking is the OEM supplied small capacity WIP stocker, that is mounted directly to the front of a process tool. Overhead Zero Foot Print microstocking is the fourth choice, which uses ceiling mounted shelves integrated directly below the overhead intrabay vehicle systems. This paper is the result of investigating these automation concepts using discrete event simulation modeling. The fat, process system model is integrated with the automation system to yield insight into the effectiveness of microstocking and overhead automation. The industry generally agrees that 300 mm fabs will be highly automated; this case study explores some of the issues facing those who implement intrabay automation.

On optimal board-level routing for FPGA-based logic emulation

Abstract: In this paper, we consider a board-level routing problem which is applicable to field-programmable gate arrays (FPGA)-based logic emulation systems such as the Realizer System and the Enterprise Emulation System manufactured by Quickturn Design Systems. For the case where all nets are two-terminal nets, we present an O(n/sup 2/)-time optimal algorithm where n is the number of nets. Our algorithm guarantees 100% routing completion if the number of interchip signal pins on each FPGA chip in the logic emulation system is less than or equal to the number of I/O pins on the chip. Our algorithm is based on iterative computation of Euler circuits in graphs. We also prove that the routing problem with multiterminal nets is NP-complete. Also we suggest one way to handle multiterminal nets using some additional resources.