Showing papers on "Electronic design automation published in 2013"

LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits

Abstract: This paper describes an innovative design automation tool, LAYGEN II, for analog integrated circuit (IC) layout generation based on template descriptions and on evolutionary computation techniques. LAYGEN II was developed giving special emphasis to the reusability of expert knowledge and to the efficiency of retargeting operations. The designer specifies the sized circuit-level structure, the required technology and also, the layout template consisting of technology and specification independent high-level layout guidelines. For placement, the topological relations present in the template are extracted to a nonslicing B*-tree layout representation, and the tool automatically merges devices and improves the floorplan quality. For routing an optimization kernel consisting of a tailored version of the multiobjective multiconstraint evolutionary algorithm NSGA-II is used. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic layout generation is demonstrated here using the LAYGEN II tool for typical analog circuit structures, and the results in GDSII format were validated using the industrial grade verification tool Calibre®.

Security-aware mapping for CAN-based real-time distributed automotive systems

Abstract: Cyber-security is a rising issue for automotive electronic systems, and it is critical to system safety and dependability. Current in-vehicles architectures, such as those based on the Controller Area Network (CAN), do not provide direct support for secure communications. When retrofitting these architectures with security mechanisms, a major challenge is to ensure that system safety will not be hindered, given the limited computation and communication resources. We apply Message Authentication Codes (MACs) to protect against masquerade and replay attacks on CAN networks, and propose an optimal Mixed Integer Linear Programming (MILP) formulation for solving the mapping problem from a functional model to the CAN-based platform while meeting both the security and the safety requirements. We also develop an efficient heuristic for the mapping problem under security and safety constraints. To the best of our knowledge, this is the first work to address security and safety in an integrated formulation in the design automation of automotive electronic systems. Experimental results of an industrial case study show the effectiveness of our approach.

AutoBioCAD: Full Biodesign Automation of Genetic Circuits

Abstract: Synthetic regulatory networks with prescribed functions are engineered by assembling a reduced set of functional elements. We could also assemble them computationally if the mathematical models of those functional elements were predictive enough in different genetic contexts. Only after achieving this will we have libraries of models of biological parts able to provide predictive dynamical behaviors for most circuits constructed with them. We thus need tools that can automatically explore different genetic contexts, in addition to being able to use such libraries to design novel circuits with targeted dynamics. We have implemented a new tool, AutoBioCAD, aimed at the automated design of gene regulatory circuits. AutoBioCAD loads a library of models of genetic elements and implements evolutionary design strategies to produce (i) nucleotide sequences encoding circuits with targeted dynamics that can then be tested experimentally and (ii) circuit models for testing regulation principles in natural systems, providing a new tool for synthetic biology. AutoBioCAD can be used to model and design genetic circuits with dynamic behavior, thanks to the incorporation of stochastic effects, robustness, qualitative dynamics, multiobjective optimization, or degenerate nucleotide sequences, all facilitating the link with biological part/circuit engineering.

Development of PLC-Based Software for Increasing the Dependability of Production Automation Systems

Abstract: This paper presents the elaboration of a concept to develop and implement real-time capable industrial automation software that increases the dependability of production automation systems by means of soft sensors. An application example with continuous behavior as it is a typical character treat of process automation is used to illustrate the initial requirements. Accordingly, the modeling concept is presented which supports application development and which is supplemented by an implementation approach for standard automation devices, e.g., programmable logic controllers. The paper further comprises an evaluation which adapts the concept for two use cases with discrete behavior (typical character treat of manufacturing automation) and validates the initially imposed requirements.

Adiabatic Logic: Future Trend and System Level Perspective - Volume 34

Abstract: Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.

The ITRS design technology and system drivers roadmap: process and status

Abstract: The Design technology working group (TWG) is one of 16 working groups in the International Technology Roadmap for Semiconductors (ITRS) effort. It is responsible for the ITRS' Design Chapter, which roadmaps design technology requirements and potential solutions for elements of the semiconductor supply chain that are produced by the electronic design automation (EDA) industry. The Design TWG is also responsible for the ITRS' System Drivers Chapter, which roadmaps the key product classes that drive the leading-edge requirements for process and design technologies. Through these activities, the Design TWG sets a number of fundamental parameters in the overall ITRS: layout density, die size, maximum on-chip clock frequency, total chip power, SOC and MPU architecture models, etc. This paper reviews the process by which the Design TWG evolves its roadmap content, and some of the key modeling and roadmapping questions that the semiconductor and EDA industries will face in the near term.

32/28nm Educational Design Kit: Capabilities, deployment and future

Abstract: An Educational Design Kit (EDK) which supports a 32/28nm design flow is described which includes all the necessary design rules, models, technology files, verification and extraction command decks, scripts, symbol libraries, and PyCells It also includes a Digital Standard Cell Library (DSCL) which supports all contemporary low power design techniques; an Standard and Special I/O Cell Libraries (IOSCL and IOSpCL); a set of memories (SOM) with different word and data depths; a set of low-power memories (SOM LP) and a phase-locked loop (PLL) These components of the EDK augment any type of design for educational and research purposes Though the EDK does not contain any foundry information, it allows 32/28nm technology with high accuracy close to real processes to be implemented in the designs

Security Analysis of Industrial Test Compression Schemes

Abstract: Test compression is widely used for reducing test time and cost of a very large scale integration circuit. It is also claimed to provide security against scan-based side-channel attacks. This paper pursues the legitimacy of this claim and presents scan attack vulnerabilities of test compression schemes used in commercial electronic design automation tools. A publicly available advanced encryption standard design is used and test compression structures provided by Synopsys, Cadence, and Mentor Graphics design for testability tools are inserted into the design. Experimental results of the differential scan attacks employed in this paper suggest that tools using X-masking and X-tolerance are vulnerable and leak information about the secret key. Differential scan attacks on these schemes have been demonstrated to have a best case success rate of 94.22% and 74.94%, respectively, for a random scan design. On the other hand, time compaction seems to be the strongest choice with the best case success rate of 3.55%. In addition, similar attacks are also performed on existing scan attack countermeasures proposed in the literature, thus experimentally evaluating their practical security. Finally, a suitable countermeasure is proposed and compared to the previously proposed countermeasures.

Approximate circuit design by means of evolvable hardware

Abstract: This paper deals with evolutionary design of approximate circuits. This class of circuits is characterized by relaxing the requirement on functional equivalence between the specification and implementation in order to reduce the area on a chip or minimize energy consumption. We proposed a CGP-based automated design method which enables to find a good trade off between key circuit parameters (functionality, area and power consumption). In particular, the digital approximate circuits consisting of elementary gates are addressed in this paper. Experimental results are provided for combinational single-output circuits and adders where two different metrics are compared for the error assessment.

Analog/RF and Mixed-Signal Circuit Systematic Design

Abstract: Despite the fact that in the digital domain, designers can take full benefits of IPs and design automation tools to synthesize and design very complex systems, the analog designers task is still considered as a handcraft, cumbersome and very time consuming process. Thus, tremendous efforts are being deployed to develop new design methodologies in the analog/RF and mixed-signal domains. This book collects 16 state-of-the-art contributions devoted to the topic of systematic design of analog, RF and mixed signal circuits. Divided in the two parts Methodologies and Techniques recent theories, synthesis techniques and design methodologies, as well as new sizing approaches in the field of robust analog and mixed signal design automation are presented for researchers and R/D engineers.

A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

Abstract: In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing process variations are included, with demonstrations on two representatives (RO and SRAM) under realistic digital circuit operations. The proposed approach and the results are helpful for robust and resilient device/circuit co-design in future nano-CMOS technology.

A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

Abstract: Applying symbolic techniques for analog circuit analysis is a traditional research subject, which has lasted for over half a century. The past decade has witnessed a significant advancement of the symbolic techniques developed specifically for large analog integrated circuits. The key methodology introduced is a data structure called binary decision diagram (BDD) which was established originally for logic design and verification. The application of the BDD technique for analog circuit analysis has the following features: (1) It is a compact data structure so that data redundancy in symbolic analysis can be eliminated. (2) It provides a mechanism for implicit enumeration method so that exhaustive enumeration commonly performed in symbolic analysis can be avoided. (3) Numerical evaluation on a BDD can be made extremely efficient, making it an excellent means for repetitive analysis. More advanced features are yet to be explored. This survey brings together the significant research results published in the past decade and provides a tutorial overview on the basic principles of applying BDD to analog circuit analysis. Some new directions that are potentially valuable for developing future analog design automation tools are discussed and a design example is given to illustrate the application of symbolic techniques.

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Abstract: The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manually-optimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.

The CRNS framework and its application to programmable and reconfigurable cryptography

Abstract: This article proposes the Computing with the ResidueNumber System (CRNS) framework, which aims at the design automation of accelerators for Modular Arithmetic (MA). The framework provides a comprehensive set of tools ranging from a programming language and respective compiler to back-ends targeting parallel computation platforms such as Graphical Processing Units (GPUs) and reconfigurable hardware. Given an input algorithm described with a high-level programming language, the CRNS can be used to obtain in a few seconds the corresponding optimized Parallel Thread Execution (PTX) program ready to be run on GPUs or the Hardware Description Language (HDL) specification of a fully functional accelerator suitable for reconfigurable hardware and embedded systems. The resulting framework's implementations benefit from the Residue Number System (RNS) arithmetic's parallelization properties in a fully automated way. Designers do not need to be familiar with the mathematical details concerning the employed arithmetic, namely the RNS representation. In order to thoroughly describe and evaluate the proposed framework, experimental results obtained for the supported back-ends (GPU and HDL) are presented targeting the implementation of the modular exponentiation used in the Rivest-Shamir-Adleman (RSA) algorithm and Elliptic Curve (EC) point multiplication. Results suggest competitive latency and throughput with minimum design effort and overcoming all the development issues that arise in the specification and verification of dedicated solutions.

cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells

Abstract: Asynchronous circuits are an attractive option to overcome many challenges currently faced by chip designers, such as increased process variation. However, the lack of CAD tools to generate asynchronous circuits limits the adoption of this promising technology. In this absence of CAD tools, the most time consuming part of chip design is the back-end (physical design) effort. We propose a complete design infrastructure to physically implement an asynchronous digital net list with orders of magnitude time savings over expert human effort. The core of this flow is the ability to generate customized logic that is compatible with available ASIC flows. We evaluate our flow against several asynchronous circuit benchmarks for which full custom physical implementations exist. Compared to hand-optimized custom designs, our flow produces layout that has, on average, a 51% area overhead, with a 12% increase in energy and a 9% increase in delay.

Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems

Abstract: Adaptive systems have the ability to respond to environmental conditions by modifying their processing at runtime. This can be implemented by using partial reconfiguration (PR) on FPGAs. However, designing such systems requires specialist architecture knowledge and an understanding of the mechanics of reconfiguration, as the design process is completely manual. One design choice that must be made, which impacts system efficiency significantly, is how to group reconfigurable modules and assign them to reconfigurable regions on the FPGA. In this paper, we present an approach, based on graph clustering, that finds a partitioning that minimises reconfiguration time, given an application description and target FPGA. The resulting allocation respects all the constraints set by the official tool flow while raising the level of design abstraction, allowing non-expert designers to leverage this capability of FPGAs.

Low power design flow based on Unified Power Format and Synopsys tool chain

Abstract: Unified Power Format (UPF) is an industry wide power format specification to implement low power techniques in a design flow. UPF is designed to reflect the power intent of a design at a relatively high level. UPF scripts help describe power intent such as: which power rails to be routed to individual blocks, when blocks are expected to be powered up or shut down, how voltage levels should be shifted between two different power domains, and type of measures taken for retention registers and memory cells contents if the primary power supply to a domain is removed, hence helping the design to be more efficient. With power becoming an important factor in today's electronic systems, there is a need for a more systematic approach to reduce power in complex designs; and UPF is developed to address this need. We have developed the complete UPF based low power design flow from high level behavioral description to physical layout. The design flow is accompanied by an example-driven and self-study tutorial suitable for hands-on teaching. The examples cover a variety of low power methods such as clock-gating, multi-voltage, power gating, and the combination of multi-voltage and power gating. This design flow is implemented using Synopsys electronic design automation tools and tested on Synopsys generic 90nm and 32/28nm libraries. The synthesis scripts are setup in `tcl' format that are compatible with the Synopsys synthesis and physical design tools.

RC extraction for single patterning spacer technique

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration

Abstract: Designers are more and more forced to define innovative models and methodologies for managing integration of heterogeneous components and heterogeneous Chip Multiprocessors (CMPs) in modern embedded systems. In this context, component-based design seems the more promising approach, but it suffers from the lack of a widely adopted Model of Computation (MoC) able to capture component heterogeneity. This paper proposes univerCM, a new model of computation based on the Heterogeneous Intermediate Format (HIF) with the aim of supporting bottom-up design and system integration from a set of heterogeneous components. HW and SW components can be described by means of different languages and according to different MoCs, toward a uniform intermediate description based on a rigorous semantics. A mapping from univerCM to SystemC is proposed then to obtain a homogeneous description intended for fast simulation, that can be also used as starting point for CMP design flows. Experimental results show the effectiveness of univerCM in managing system heterogeneity.

An EDA-friendly protection scheme against side-channel attacks

Abstract: This paper introduces a generic and automated methodology to protect hardware designs from side-channel attacks in a manner that is fully compatible with commercial standard cell design flows. The paper describes a tool that artificially adds jitter to the clocks of the sequential elements of a cryptographic unit, which increases the non-determinism of signal timing, thereby making the physical device more difficult to attack. Timing constraints are then specified to commercial EDA tools, which restore the circuit functionality and efficiency while preserving the introduced randomness. The protection scheme is applied to an AES-128 hardware implementation that is synthesized using both ASIC and FPGA design flows.

A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits

Abstract: This text addresses the design methodologies and CAD tools available for the systematic design and design automation of analogue integrated circuits. Two complementary approaches discussed increase analogue design productivity, demonstrated throughout using design times of the different design experiments undertaken.

21st century digital design tools

Abstract: Most chips today are designed with 20th century CAD tools. These tools, and the abstractions they are based on, were originally intended to handle designs of millions of gates or less. They are not up to the task of handling today's billion-gate designs. The result is months of delay and considerable labor from final RTL to tapeout. Surprises in timing closure, global congestion, and power consumption are common. Even taking an existing design to a new process node is a time-consuming and laborious process.Twenty-first century CAD tools should be based on higher-level abstractions to enable billion-gate chips to go from final RTL to tapeout in days, not months. Key to attaining this increase in productivity is raising the level of design and using simple, standard interfaces. Designs should be composed from high-level modules -- processors, MODEMs, CODECs, memory subsystems, and I/O subsystems -- rather than gates and flip-flops. Each module, which we expect to contain 100 thousand to 10 million gates, is easily laid out by today's tools, is placed as a unit, and communicates over a NoC via a standard interface. Restricting modules to standard sizes and aspect ratios further simplifies physical design. We expect even a large chip to contain at most a few thousand such modules and expect the physical design and chip-assembly to take a few days with minimal labor after completion of the module-level design.

Compression method and system for use with multi-patterning

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

A verilog-a model for reconfigurable logic gates based on graphene pn-junctions

Abstract: Single layer sheets of graphene show special electrical properties that can enable the next generation of smart ICs Recent works have proven the availability of an electrostatically controlled pn-junction upon which it is possible to design multi-function reconfigurable logic devices that naturally behave as multiplexers In this work we introduce a stable large-signal Verilog-A model that mimics the behavior of the aforementioned devices The proposed model, validated through the SPICE characterization of a MUX-based standard cell library we designed as benchmark, represents a first step towards the integration of Electronic Design Automation tools that can support the design of all-graphene ICs

High-level synthesis of multiple dependent CUDA kernels on FPGA

Abstract: High-level synthesis (HLS) tools provide automatic generation of hardware at the register transfer level (RTL) from algorithm descriptions written in high-level languages, enabling faster creation of custom accelerators for FPGA architectures. Existing HLS tools support a wide variety of input languages, and assist users in design space exploration through automation and feedback on designs' performance bottlenecks. This design space exploration applies techniques such as pipelining, partitioning and resource sharing in order to improve performance, and resource utilization. However, although automated exploration can find some inherent parallelism, data-parallel input source code is still superior for exposing a greater variety of parallelism. In prior work, we demonstrated automated design space exploration of GPU multi-threaded (CUDA) language source code for efficient RTL generation. In this paper, we examine the challenges in extending this automated design space exploration to multiple dependent CUDA kernels, demonstrate a step-by-step procedure for efficiently performing multi-kernel synthesis, and demonstrate the potential of this approach through a case study of a stereo matching algorithm. This study demonstrates that HLS of multiple dependent CUDA kernels can maintain performance parity with the GPU implementation, while consuming over 16X less energy than the GPU. Based on our manual procedure, we identify the key challenges in fully automating the synthesis of multi-kernel CUDA programs.

Improving the link between computer-assisted design and configuration tools for the design of mechanical products

Abstract: The competitive market forces companies to offer tailored products to meet specific customer needs. To avoid wasting time, design efforts generally address the configuration of existing solutions, without producing substantial design modifications. Configuration tools are used to achieve customized products starting from a common platform. Many approaches have been successfully proposed in literature to configure products. However, in the mechanical field they need further investigation in order to be efficiently linked to computer-aided design technologies. Research is focused on tools and methods to automatically produce geometrical models and improve the flexibility of the continuous product updating process. In this context, this paper aims to combine product configuration approaches with design automation techniques in order to support design activities of products to fulfill specific requirements. The approach is based on entities called configurable virtual prototypes. Three different domains are managed and connected via configurable virtual prototypes: product specifications, geometrical data, and product knowledge. In particular, geometry recognition rules are used to identify the parameterization of parts and the assembly mating constraints. The approach is exemplified through an industrial case study where a tool has been developed on the basis of the described method. Advantages of the system are shown in terms of achieved product configuration efficiency.

Dynamic modeling of cellular populations within iBioSim.

Abstract: As the complexity of synthetic genetic circuits increases, modeling is becoming a necessary first step to inform subsequent experimental efforts. In recent years, the design automation community has developed a wealth of computational tools for assisting experimentalists in designing and analyzing new genetic circuits at several scales. However, existing software primarily caters to either the DNA- or single-cell level, with little support for the multicellular level. To address this need, the iBioSim software package has been enhanced to provide support for modeling, simulating, and visualizing dynamic cellular populations in a two-dimensional space. This capacity is fully integrated into the software, capitalizing on iBioSim’s strengths in modeling, simulating, and analyzing single-celled systems.

A Verilog-A model for silicon nanowire biosensors: From theory to verification

Abstract: Silicon nanowires offer great potential as highly sensitive biosensors. Since the signals they produce are quite weak and noisy, the use of integrated circuits is preferable to read out and digitize these signals as quickly as possible following the sensing event to take full advantage of the properties of the nanowires. In order to design optimized and tailored circuits, simulations involving the sensor itself in the design phase are needed. We propose here a Verilog-A model for silicon nanowire-based biosensors. The model can easily be applied using commercially available electronic design automation (EDA) tools that are commonly used for integrated circuit design and simulations. The model is quite general and comprehensive; it can be used to simulate different types of sensing events, while still being quite simple and undemanding in terms of computational power. The model is described in detail and verified with measurements from two different nanowire sensors featuring aluminum-oxide and hafnium-oxide coatings. Good agreement has been achieved in all cases, with errors never exceeding 21%.