Showing papers on "Electronic design automation published in 2016"

Genetic circuit design automation

Abstract: INTRODUCTION Cells respond to their environment, make decisions, build structures, and coordinate tasks. Underlying these processes are computational operations performed by networks of regulatory proteins that integrate signals and control the timing of gene expression. Harnessing this capability is critical for biotechnology projects that require decision-making, control, sensing, or spatial organization. It has been shown that cells can be programmed using synthetic genetic circuits composed of regulators organized to generate a desired operation. However, the construction of even simple circuits is time-intensive and unreliable. RATIONALE Electronic design automation (EDA) was developed to aid engineers in the design of semiconductor-based electronics. In an effort to accelerate genetic circuit design, we applied principles from EDA to enable increased circuit complexity and to simplify the incorporation of synthetic gene regulation into genetic engineering projects. We used the hardware description language Verilog to enable a user to describe a circuit function. The user also specifies the sensors, actuators, and “user constraints file” (UCF), which defines the organism, gate technology, and valid operating conditions. Cello (www.cellocad.org) uses this information to automatically design a DNA sequence encoding the desired circuit. This is done via a set of algorithms that parse the Verilog text, create the circuit diagram, assign gates, balance constraints to build the DNA, and simulate performance. RESULTS Cello designs circuits by drawing upon a library of Boolean logic gates. Here, the gate technology consists of NOT/NOR logic based on repressors. Gate connection is simplified by defining the input and output signals as RNA polymerase (RNAP) fluxes. We found that the gates need to be insulated from their genetic context to function reliably in the context of different circuits. Each gate is isolated using strong terminators to block RNAP leakage, and input interchangeability is improved using ribozymes and promoter spacers. These parts are varied for each gate to avoid breakage due to recombination. Measuring the load of each gate and incorporating this into the optimization algorithms further reduces evolutionary pressure. Cello was applied to the design of 60 circuits for Escherichia coli , where the circuit function was specified using Verilog code and transformed to a DNA sequence. The DNA sequences were built as specified with no additional tuning, requiring 880,000 base pairs of DNA assembly. Of these, 45 circuits performed correctly in every output state (up to 10 regulators and 55 parts). Across all circuits, 92% of the 412 output states functioned as predicted. CONCLUSION Our work constitutes a hardware description language for programming living cells. This required the co-development of design algorithms with gates that are sufficiently simple and robust to be connected by automated algorithms. We demonstrate that engineering principles can be applied to identify and suppress errors that complicate the compositions of larger systems. This approach leads to highly repetitive and modular genetics, in stark contrast to the encoding of natural regulatory networks. The use of a hardware-independent language and the creation of additional UCFs will allow a single design to be transformed into DNA for different organisms, genetic endpoints, operating conditions, and gate technologies.

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family

Abstract: Recent advances in Neural Networks (NN) are enabling more and more innovative applications. As an energy-efficient hardware solution, machine learning accelerators for CNNs or traditional ANNs are also gaining popularity in the area of embedded vision, robotics and cyberphysics. However, the design parameters of NN models vary significantly from application to application. Hence, it's hard to provide one general and highly-efficient hardware solution to accommodate all of them, and it is also impractical for the domain-specific developers to customize their flown hardware targeting on a specific NN model. To deal with this dilemma, this study proposes a design automation tool, DeepBurning, allowing the application developers to build from scratch learning accelerators that targets their specific NN models with custom configurations and optimized performance. DeepBurning includes a RTL-level accelerator generator and a coordinated compiler that generates the control flow and data layout under the user-specified constraints. The results can be used to implement FPGA-based NN accelerator or help generate chip design for early design stage. In general, DeepBurning supports a large family of NN models, and greatly simplifies the design flow of NN accelerators for the machine learning or AI application developers. The evaluation shows that the generated learning accelerators burnt to our FPGA board exhibit great power efficiency compared to state-of-the-art FPGA-based solutions.

3-D-Printed Air-Core Inductors for High-Frequency Power Converters

Abstract: This paper presents the design, modeling, and characterization of 3-D-printed air-core inductors for high-frequency power electronics circuits. The use of 3-D modeling techniques to make passive components extends the design flexibility and addresses some of the fabrication limitations of traditional processes. Recent work [1] – [9] has demonstrated the feasibility of incorporating air-core inductors in high-frequency ( $>$ 10 MHz) switching power converters. These implementations have used discrete wire wound solenoids and toroids, and planar components that use printed circuit board traces or microfabrication techniques to make air-core inductors. However, realizations of such components have limitations in performance and applicability including open paths conducive to the flow of leakage fields, and difficulties in achieving optimal cross section to minimize loss. Along with the current effort of involving 3-D printing technology to make inductors [10] , [11] , we propose the use of 3-D printing and casting/plating techniques as a simple and accessible alternative that adds flexibility and functionality to the air-core inductor design for high-frequency power conversion at moderate to high-power (e.g., tens to thousands of watts) and high-voltage (greater than 100 V) levels. In this paper, we present several examples of air-core inductors realized using 3-D printing and casting/plating techniques to give an idea of the geometries that are possible to design. Moreover, we show that some of these designs can lead to improved electrical performance. This paper also describes the tools used by the authors to design, fabricate, and characterize the electromagnetic performance of the air-core inductors. The software used to generate the 3-D scaffolds for the inductors are freely available and easily accessible. Readers are encouraged to explore more possibilities of geometries that can lead to better performance with the ease of manufacturing. As progress in additive manufacturing continues, we envision 3-D printing of a complete scaffold structure that after plating (or casting) will contain all resonant passive components of an RF switching converter. Toward this goal, we present a 70-W prototype 27.12-MHz resonant inverter that incorporates some of the 3-D-printed components developed for this paper.

Recent research development and new challenges in analog layout synthesis

Abstract: Analog and mixed-signal integrated circuits play an important role in many modern emerging system-on-chip (SoC) design applications. With the expansion of the markets of those applications, the demands of analog/mixed-signal ICs have been dramatically increased. Although analog/mixed-signal ICs have gained more and more importance and demands in modern SoC applications, the development of analog electronic design automation (EDA) tools is still farther behind that of digital EDA tools. As a result, analog/mixed-signal IC design, especially the analog layout design, is still a manual, time-consuming, and error-prone task. In order to speed up modern SoC design for large varieties of emerging applications, it is desirable to develop novel analog/mixed-signal IC deign methodologies and algorithms, as well as new analog EDA tools. The purpose of this paper is to summarize recent research progress during the past decade, address new analog layout design challenges in advanced technology nodes, and facilitate more research activities in analog layout synthesis.

Resource-aware Automotive Control Systems Design: A Cyber-Physical Systems Approach

Abstract: As the automotive industry is entering the smart era through advancesin sensing, computation, storage, communication, and actuation technologies,a larger number of more complex control applications withbetter performances are expected to be on board. This requires an implementationplatform with abundant resources, which is undesired inthe cost-sensitive automotive domain. The implementation platform,often embedded in an Electronic Control Unit ECU and shared bymultiple applications to save cost, is mainly comprised of a processorfor computation, memory for storing instructions and data, and busfor internal and external communication. Conventionally, automotivecontrol systems are designed using model-based approaches, where thedetails of the implementation platform are ignored. Techniques thatintegrate the characteristics of implementation resources into controlalgorithms design are largely missing. Such a separate design paradigmis too conservative in resources dimensioning and utilization for modernvehicles. This article presents recently developed approaches in automotivecontrol systems design that take implementation resources intoconsideration, aiming to improve the control performances for a givenamount of resources, or equivalently, realize the required control performanceswith fewer resources. While communication resources have beenextensively explored in the literature of networked embedded controlsystems, we will focus on memory and computation resources, whichhave started to receive attention from the academic community andindustry just recently. As Electric Vehicles EVs have become a newtrend in the automotive industry, energy resources of EVs, i.e., thebatteries, are also investigated. A number of real-world applicationsvalidate the resource-aware automotive systems design techniques presentedin this article.

Design Tools for Rapid Multidomain Virtual Prototyping of Power Electronic Systems

Abstract: The need for multidisciplinary virtual prototyping in power electronics has been well established, however, design tools capable of facilitating a rapid iterative virtual design process do not exist. A key challenge in developing such tools is identifying and developing modeling techniques which can account for 3-D geometrical design choices without unduly affecting simulation speed. This challenge has been addressed in this paper using model order reduction techniques and a prototype power electronic design tool incorporating these techniques is presented. A relevant electrothermal power module design example is then used to demonstrate the performance of the software and model order reduction techniques. Five design iterations can be evaluated, using 3-D inductive and thermal models, under typical operating and start-up conditions on a desktop PC in less than 15 min. The results are validated experimentally for both thermal and electrical domains.

A Methodology for Standard Cell Design for QCA

Abstract: QCA (Quantum-Dot Cellular Automata) is an emerging nanotechnology that has the potential to replace current CMOS technologies. QCA permits extremely low power consumption, since its working principle is not based on electric current flow but on Coulomb interaction. The development of Electronic Design Automation (EDA) tools and flows is an essential step towards the applicability of QCA for integrated designs. However, the scarce number of works in this field highlights that there is plenty of room for the development of new EDA methodologies for emerging nanotechnologies. Standard cells play an important role in this context, since the development of routing and placement algorithms are strongly related to their existence. This work presents a methodology for standard cell design for QCA as well as the exemplary QCA cell library ONE, which is based on the recently proposed USE (Universal, Scalar and Efficient) clocking scheme. Two representative case studies indicate the feasibility of the approach.

Microwave and Millimetre-Wave Design for Wireless Communications

Abstract: This book describes a full range of contemporary techniques for the design of transmitters and receivers for communications systems operating in the range from 1 through to 300 GHz. In this frequency range there is a wide range of technologies that need to be employed, with silicon ICs at the core but, compared with other electronics systems, a much greater use of more specialist devices and components for high performance – for example, high Q-factor/low loss and good power efficiency. Many text books do, of course, cover these topics but what makes this book timely is the rapid adoption of millimetre-waves (frequencies from 30 to 300 GHz) for a wide range of consumer applications such as wireless high definition TV, “5G” Gigabit mobile internet systems and automotive radars. It has taken many years to develop low-cost technologies for suitable transmitters and receivers, so previously these frequencies have been employed only in expensive military and space applications. The book will cover these modern technologies, with the follow topics covered; transmitters and receivers, lumped element filters, tranmission lines and S-parameters, RF MEMS, RFICs and MMICs, and many others. In addition, the book includes extensive line diagrams to illustrate circuit diagrams and block diagrams of systems, including diagrams and photographs showing how circuits are implemented practically. Furthermore, case studies are also included to explain the salient features of a range of important wireless communications systems. The book is accompanied with suitable design examples and exercises based on the Advanced Design System – the industry leading CAD tool for wireless design. More importantly, the authors have been working with Keysight Technologies on a learning & teaching initiative which is designed to promote access to industry-standard EDA tools such as ADS. Through its University Educational Support Program, Keysight offers students the opportunity to request a student license, backed up with extensive classroom materials and support resources. This culminates with students having the chance to demonstrate their RF/MW design and measurement expertise through the Keysight RF & Microwave Industry-Ready Student Certification Program.

Analysis And Design Of Digital Integrated Circuits

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Knowledge based engineering as a condition of effective mass production of configurable products by design automation

Abstract: The paper presents possibilities of improving design and manufacturing preparation processes of configurable (variant) products in scope of realization of mass customization strategy. Knowledge based engineering tools are presented as a base for building systems for automation of design and manufacturing preparation. Methodologies of building KBE systems are presented and described, authors’ own methodology is presented along with selected cases of its use. It is proven that reduction of time needed for design and manufacturing preparation can be vast, justifying use of KBE systems as a way of manufacturing optimization of configurable products.

Automatic Wire-Routing of SFQ Digital Circuits Considering Wire-Length Matching

Abstract: An automatic wire-routing method of passive transmission lines (PTLs) for single-flux-quantum digital circuits is proposed. The method considers the wire routing of a rectangular region between adjacent columns of active devices. To perform wire routing considering the difference between the timing variabilities of active devices and those of PTLs, the proposed wire-routing method provides paths of PTLs with a specified additional length for delay insertion. The problem is formulated as integer linear programming. Experimental results show that compact layouts are obtained.

Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations

Abstract: Microfluidic biochips are being used to perform ever more complex and error-prone bioassays. This results in increasing demand for design automation for such biochips, as these sophisticated designs are beyond the scope of manual design. So far, much research in the field of design automation has been devoted to satisfy this demand from biology, but the gap between design automation and biology is still huge. To narrow this gap, we propose a synthesis method in which sieve valves, which are key components in flow-based microfluidic biochips, are considered for the first time. In addition, we integrate three more constraints into our synthesis that are commonly seen in bioassays but have so far been neglected by design automation: immediate execution, mutual exclusion, and parallel execution. Experiments show that compared with traditional synthesis, this new method shows significant improvements, and the gap between design automation and biology is getting bridged.

Accelerating Workloads on FPGAs via OpenCL: A Case Study with OpenDwarfs

Abstract: For decades, the streaming architecture of FPGAs has delivered accelerated performance across many application domains, such as option pricing solvers in finance, computational fluid dynamics in oil and gas, and packet processing in network routers and firewalls. However, this performance comes at the expense of programmability. FPGA developers use hardware design languages (HDLs) to implement the application data and control path and to design hardware modules for computational pipelines, memory management, synchronization, and communication. This process requires extensive knowledge of logic design, design automation tools, and low-level details of FPGA architecture, this consumes significant development time and effort. To address this lack of programmability of FPGAs, OpenCL provides an easy-to-use and portable programming model for CPUs, GPUs, APUs, and now, FPGAs. Although this significantly improved programmability yet an optimized GPU implementation of kernel may lack performance portability for FPGA. To improve the performance of OpenCL kernels on FPGAs we identify general techniques to optimize OpenCL kernels for FPGAs under device-specific hardware constraints. We then apply these optimizations techniques to the OpenDwarfs benchmark suite, which has diverse parallelism profiles and memory access patterns, in order to evaluate the effectiveness of the optimizations in terms of performance and resource utilization. Finally, we present the performance of structured grids and N-body dwarf-based benchmarks in the context of various optimization along with their potential re-factoring. We find that careful design of kernels for FPGA can result in a highly efficient pipeline achieving 91% of theoretical throughput for the structured grids dwarf.

A Systematic Design Methodology of Asynchronous SAR ADCs

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent power efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also hard to quickly evaluate the feasibility of a given specification in a process node. This paper presents a systematic sizing procedure for asynchronous SAR ADCs based on design considerations. A sizing tool based on the proposed design procedure is also implemented, the sizing results of which are highly competitive in comparison with other state-of-the-art manual works. Moreover, the sizing time is relatively short due to the efficient and effective search algorithms employed. In addition to the simulation results, two silicon proofs with different specifications and process nodes are provided to demonstrate the feasibility of this design methodology.

Physical Design Automation for 3D Chip Stacks: Challenges and Solutions

Abstract: The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality and power consumption going forward. However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips. We survey major design challenges for 3D chip stacks with particular focus on their implications for physical design. We also derive requirements for advances in design automation, such as the need for a unified workflow. Finally, we outline current promising solutions as well as areas needing further research and development.

Comprehensive path based analysis process

Abstract: The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis (“GBA”) violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis (“PBA”) on the worst timing path and determining if the worst timing path satisfies the PBA analysis.

Delay-optimal technology mapping for in-memory computing using ReRAM devices

Abstract: Recent propositions of diverse In-Memory Computing platforms have shown a promising alternative to classical Von Neumann computing models. Significant benefits, in terms of energy-efficiency and performance, are reported for in-memory arithmetic circuits, neural networks, CAM, cache hierarchy and even fully programmable processors. In contrast, design automation tools supporting the development of such designs are still in a nascent phase. By leveraging the native stateful logic operation capability of ReRAM devices, several logic synthesis flows have been reported. In this paper, we complement these flows with a detailed study on the technology mapping phase for ReRAM devices. We provide a delay-optimal solution for technology mapping without area constraint and propose further heuristics to achieve device count reduction and to support delay optimization under the constraint of parallel instruction dispatch. We report at least 3× less delay compared to the naive technology mapping adopted in recent studies. The proposed heuristics achieve 56% on average reduction in device count. Finally, a range of performance trade-offs is identified by applying the constraint of parallel instruction dispatch without noticeable degradation of delay.

Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing

Abstract: RRAM-based approximate computing systems are significantly more energy efficient than many digital approximate computing systems, but their accuracy is less easily controlled and quantified. This paper analyzes the precision limitation for such systems and highlights the importance of RRAM device resolution in low-resistance states.

Mapping Generative Models onto a Network of Digital Spiking Neurons

Abstract: Stochastic neural networks such as Restricted Boltzmann Machines (RBMs) have been successfully used in applications ranging from speech recognition to image classification, and are particularly interesting because of their potential for generative tasks. Inference and learning in these algorithms use a Markov Chain Monte Carlo procedure called Gibbs sampling, where a logistic function forms the kernel of this sampler. On the other side of the spectrum, neuromorphic systems have shown great promise for low-power and parallelized cognitive computing, but lack well-suited applications and automation procedures. In this work, we propose a systematic method for bridging the RBM algorithm and digital neuromorphic systems, with a generative pattern completion task as proof of concept. For this, we first propose a method of producing the Gibbs sampler using bio-inspired digital noisy integrate-and-fire neurons. Next, we describe the process of mapping generative RBMs trained offline onto the IBM TrueNorth neurosynaptic processor—a low-power digital neuromorphic VLSI substrate. Mapping these algorithms onto neuromorphic hardware presents unique challenges in network connectivity and weight and bias quantization, which, in turn, require architectural and design strategies for the physical realization. Generative performance is analyzed to validate the neuromorphic requirements and to best select the neuron parameters for the model. Lastly, we describe a design automation procedure which achieves optimal resource usage, accounting for the novel hardware adaptations. This work represents the first implementation of generative RBM inference on a neuromorphic VLSI substrate.

OpenDesign flow database: the infrastructure for VLSI design and design automation research

Abstract: Recently, there have been a slew of design automation contests and released benchmarks. ISPD place & route contests, DAC placement contests, timing analysis contests at TAU and CAD contests at ICCAD are good examples in the past and more of new contests are planned in the upcoming conferences. These are interesting and important events that stimulate the research of the target problems and advance the cutting edge technologies. Nevertheless, most contests focus only on the point tool problems instead of addressing the design flow or co-optimization among design tools. OpenDesign Flow Database platform is developed to direct attentions to the overall design flow from logic synthesis to physical design optimization [1]. The goals are to provide an academic reference design flow based on past CAD contest results, the database for design benchmarks and point tool libraries, and standard design input/output formats to build a customized design flow by composing point tool libraries.

Estimating the Potential of State of the Art Design Automation - Tasks, Methods, and Benefits

Abstract: Industrial application of design automation is rare due to a lack of understanding about what type of tasks can be automated, what methods are available and what potential benefits can be expected. It is often difficult up-front to predict the potential savings and improvements that design automation can yield in comparison to the investment cost of its implementation. To improve this situation, this paper introduces an approach that allows mapping of design tasks characterized by spatial aspects to design automation methods and an implicit mapping of automation methods to potential benefits.