Topic
Electronic design automation
About: Electronic design automation is a research topic. Over the lifetime, 6926 publications have been published within this topic receiving 92299 citations. The topic is also known as: EDA & electronic computer-aided design.
Papers published on a yearly basis
Papers
More filters
TL;DR: In this paper, a tool for tackling the problem of robust control in the controller parameter space K is introduced, which allows determining the regions in the K space, which place all eigenvalues in the desired region in the eigenvalue plane.
Abstract: Find a state or output feedback with fixed gains such that nice stability (defined by a region in the eigenvalue plane) is robust with respect to large plant parameter variations, sensor failures, and quantization effects in the controller. Keep the required magnitude of control inputs small in this design. A tool for tackling such problems by design in the controller parameter space K is introduced. Pole placement is formulated as an affine map from the space P of characteristic polynomial coefficients to the K space. This allows determining the regions in the K space, which place all eigenvalues in the desired region in the eigenvalue plane. Then tradeoffs among a variety of different design specifications can be made in K space. The use of this tool is illustrated by the design of a crane control system. Several open research problems result from this approach: graphical computer-aided design of robust systems, algebraic robustness conditions, and algorithms for iterative design of robust control systems.
318 citations
IBM1
TL;DR: The ISPD98 benchmark suite is introduced which consists of 18 circuits with sizes ranging from 13,000 to 210,000 modules and Experimental results for three existing partitioners are presented so that future researchers in partitioning can more easily evaluate their heuristics.
Abstract: From 1985-1993, the MCNC regularly introduced and maintained circuit benchmarks for use by the Design Automation community. However, during the last five years, no new circuits have been introduced that can be used for developing fundamental physical design applications, such as partitioning and placement. The largest circuit in the existing set of benchmark suites has over 100,000 modules, but the second largest has just over 25,000 modules, which is small by today's standards. This paper introduces the ISPD98 benchmark suite which consists of 18 circuits with sizes ranging from 13,000 to 210,000 modules. Experimental results for three existing partitioners are presented so that future researchers in partitioning can more easily evaluate their heuristics.
318 citations
TL;DR: Three generations of Alpha microprocessors have been designed using a proven custom design methodology that facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths.
Abstract: Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design. The Alpha instruction set architecture facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths. Digital has developed six generations of CMOS technology optimized for high-frequency design. Complex circuit styles were used extensively to meet aggressive cycle time goals. CAD tools were developed internally to support these designs. This paper discusses some of the technologies that have enabled Alpha microprocessors to achieve high performance.
317 citations
03 Jun 2012
TL;DR: This work proposes SALSA, a Systematic methodology for Automatic Logic Synthesis of Approximate circuits, which encodes the quality constraints using logic functions called Q-functions, and captures the flexibility that they engender as Approximation Don't Cares, which are used for circuit simplification using traditional don't care based optimization techniques.
Abstract: Approximate computing has emerged as a new design paradigm that exploits the inherent error resilience of a wide range of application domains by allowing hardware implementations to forsake exact Boolean equivalence with algorithmic specifications. A slew of manual design techniques for approximate computing have been proposed in recent years, but very little effort has been devoted to design automation. We propose SALSA, a Systematic methodology for Automatic Logic Synthesis of Approximate circuits. Given a golden RTL specification of a circuit and a quality constraint that defines the amount of error that may be introduced in the implementation, SALSA synthesizes an approximate version of the circuit that adheres to the pre-specified quality bounds. We make two key contributions: (i) the rigorous formulation of the problem of approximate logic synthesis, enabling the generation of circuits that are correct by construction, and (ii) mapping the problem of approximate synthesis into an equivalent traditional logic synthesis problem, thereby allowing the capabilities of existing synthesis tools to be fully utilized for approximate logic synthesis. In order to achieve these benefits, SALSA encodes the quality constraints using logic functions called Q-functions, and captures the flexibility that they engender as Approximation Don't Cares (ADCs), which are used for circuit simplification using traditional don't care based optimization techniques. We have implemented SALSA using two off-the-shelf logic synthesis tools — SIS and Synopsys Design Compiler. We automatically synthesize approximate circuits ranging from arithmetic building blocks (adders, multipliers, MAC) to entire datapaths (DCT, FIR, IIR, SAD, FFT Butterfly, Euclidean distance), demonstrating scalability and significant improvements in area (1.1X to 1.85X for tight error constraints, and 1.2X to 4.75X for relaxed error constraints) and power (1.15X to 1.75X for tight error constraints, and 1.3X to 5.25X for relaxed error constraints).
316 citations
01 Jul 2020
TL;DR: The development of neuro-inspired computing chips and their key benchmarking metrics are reviewed, providing a co-design tool chain and proposing a roadmap for future large-scale chips are provided and a future electronic design automation tool chain is proposed.
Abstract: The rapid development of artificial intelligence (AI) demands the rapid development of domain-specific hardware specifically designed for AI applications. Neuro-inspired computing chips integrate a range of features inspired by neurobiological systems and could provide an energy-efficient approach to AI computing workloads. Here, we review the development of neuro-inspired computing chips, including artificial neural network chips and spiking neural network chips. We propose four key metrics for benchmarking neuro-inspired computing chips — computing density, energy efficiency, computing accuracy, and on-chip learning capability — and discuss co-design principles, from the device to the algorithm level, for neuro-inspired computing chips based on non-volatile memory. We also provide a future electronic design automation tool chain and propose a roadmap for the development of large-scale neuro-inspired computing chips. This Review Article examines the development of neuro-inspired computing chips and their key benchmarking metrics, providing a co-design tool chain and proposing a roadmap for future large-scale chips.
303 citations